1,720,973 research outputs found
Multi-criteria optimization for energy-efficient multi-core systems-on-chip
Get PDFThe steady down-scaling of transistor dimensions has made possible the evolutionary progress leading to today’s high-performance multi-GHz microprocessors and core based System-on-Chip (SoC) that offer superior performance, dramatically reduced cost per function, and much-reduced physical size compared to their predecessors. On the negative side, this rapid scaling however also translates to high power densities, higher operating temperatures and reduced reliability making it imperative to address design issues that have cropped up in its wake. In particular, the aggressive physical miniaturization have increased CMOS fault sensitivity to the extent that many reliability constraints pose threat to the device normal operation and accelerate the onset of wearout-based failures. Among various wearout-based failure mechanisms, Negative biased temperature instability (NBTI) has been recognized as the most critical source of device aging.
The urge of reliable, low-power circuits is driving the EDA community to develop new design techniques, circuit solutions, algorithms, and software, that can address these critical issues. Unfortunately, this challenge is complicated by the fact that power and reliability are known to be intrinsically conflicting metrics: traditional solutions to improve reliability such as redundancy, increase of voltage levels, and up-sizing of critical devices do contrast with traditional low-power solutions, which rely on compact architectures, scaled supply voltages, and small devices.
This dissertation focuses on methodologies to bridge this gap and establishes an important link between low-power solutions and aging effects. More specifically, we proposed new architectural solutions based on power management strategies to enable the design of low-power, aging aware cache memories.
Cache memories are one of the most critical components for warranting reliable and timely operation. However, they are also more susceptible to aging effects. Due to symmetric structure of a memory cell, aging occurs regardless of the fact that a cell (or word) is accessed or not. Moreover, aging is a worst-case matric and line with worst-case access pattern determines the aging of the entire cache. In order to stop the aging of a memory cell, it must be put into a proper idle state when a cell (or word) is not accessed which require proper management of the idleness of each atomic unit of power management.
We have proposed several reliability management techniques based on the idea of cache partitioning to alleviate NBTI-induced aging and obtain joint energy and lifetime benefits. We introduce graceful degradation mechanism which allows different cache blocks into which a cache is partitioned to age at different rates. This implies that various sub-blocks become unreliable at different times, and the cache keeps functioning with reduced efficiency. We extended the capabilities of this architecture by integrating the concept of reconfigurable caches to maintain the performance of the cache throughout its lifetime. By this strategy, whenever a block becomes unreliable, the remaining cache is reconfigured to work as a smaller size cache with only a marginal degradation of performance.
Many mission-critical applications require guaranteed lifetime of their operations and therefore the hardware implementing their functionality. Such constraints are usually enforced by means of various reliability enhancing solutions mostly based on redundancy which are not energy-friendly. In our work, we have proposed a novel cache architecture in which a smart use of cache partitions for redundancy allows us to obtain cache that meet a desired lifetime target with minimal energy consumption
Energy/lifetime cooptimization by cache partitioning with graceful performance degradation
No full textAging of transistors can adversely impact the long-term reliability of devices in subnanometric technologies.
Without any countermeasure, the first component that becomes unreliable will determine the life span of an entire device. The effect is more susceptible in memory arrays, where failure of a single SRAM cell would cause the failure of the whole system.
In this paper, we propose a reliability management technique based on the idea of cache partitioning, which deals with cell failures by gracefully degrading its performance.
By this partitioning-based strategy, various subblocks will become unreliable at different times, and the cache will keep functioning with reduced efficiency.
A coarse-grain implementation of this approach, with the use of a smart aging-driven partitioning algorithm, provides a lifetime extension of more than 2x.
On the other hand, a fine-grain strategy with a single cache line as a unit of power management, stretch the lifetime to its maximum limits with an addition of small hardware overhead
Mechanical properties and strain monitoring of glass-epoxy composites with graphene-coated fibers
Full text linkAn engineered interphase can improve the mechanical properties of epoxy/glass composites simultaneously inducing a piezoresistive response. To prove this concept, E-glass fibers were coated with graphene oxide (GO) by electrophoretic deposition, while reduced graphene oxide (rGO) coated fibers were obtained by subsequent chemical reduction. The fiber-matrix interfacial shear strength (measured by the single-fiber fragmentation test) increased for both GO and rGO coated fibers. Unidirectional composites with a high content of both uncoated and coated fibers were produced and mechanically tested under various configurations (three-point bending, short beam shear and mode-I fracture toughness, creep). Composites with coated fibers performed similarly or better than composites prepared with uncoated fibers. Finally, composites with rGO coated fibers were tested for their piezoresistive response under both static and dynamic conditions. The electrical resistance changed proportionally to applied strain thus confirming the possibility of using composites with rGO coated fibers as strain sensors in load-bearing components
Enhancement of interfacial adhesion in glass fiber/epoxy composites by electrophoretic deposition of graphene oxide on glass fibers
Full text linkNMP is supported by the European Research Council (ERC StG Ideas 2011 BIHSNAM no. 279985 on “Bio-Inspired Hierarchical Super Nanomaterials”, ERC PoC 2015 SILKENE no. 693670 on “Bionic silk with graphene or other nanomaterials spun by silkworms”, ERC PoC 2013-II KNOTOUGH no. 632277 on “Super-tough knotted fibres”), by the European Commission under the Graphene Flagship (WP10 “Nanocomposites”, no. 604391) and by the Provincia Autonoma di Trento (“Graphene nanocomposites”, no. S116/2012–242637 and reg. delib. no. 2266)
Aging-Aware Caches with Graceful Degradation of Performance
No full textAging of transistors can substantially shorten the lifetime of devices in sub-nanometric technologies. Without any countermeasure, the first component which becomes unreliable will determine the life span of an entire device. This problem is even more relevant for memory arrays, where failure of a single SRAM cell would cause the failure of the whole system. Traditional implementation of power management by turning idle cache lines into a low-energy state can also mitigate the aging effects caused by Negative Bias Temperature Instability (NBTI) provided that idleness is correctly exploited. In this work, we propose a cache structure which deals with cell failures by gracefully degrading its performance. By this partitioning-based strategy, various sub-blocks will become unreliable at different times, and the cache will keep functioning with reduced efficiency. Coupling such aging mitigation with the resulting energy reduction techniques we can obtain up to 2.5x lifetime extension and 40% energy savings with respect to a power managed cach
Determinants of maturity transformation risk in Islamic banks: a perspective of Basel III liquidity regulations
No full text
Going Beyond Counting First Authors in Author Co-citation Analysis
Full text linkThe present study examines one of the fundamental aspects of author co-citation analysis (ACA) - the way co-citation
counts are defined. Co-citation counting provides the data on which all subsequent statistical analyses and mappings
are based, and we compare ACA results based on two different types of co-citation counting - the traditional type that
only counts the first one among a cited work's authors on the one hand and a non-traditional type that takes into
account the first 5 authors of a cited work on the other hand. Results indicate that the picture produced through this non-traditional author co-citation counting contains more coherent author groups and is therefore considerably clearer. However, this picture represents fewer specialties in the research field being studied than that produced through the traditional first-author co-citation counting when the same number of top-ranked authors is selected and analyzed. Reasons for these effects are discussed
- …
