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Dispositivi MOSFET con Canale in InGaAs per l’Estensione della Tecnologia CMOS oltre il Nodo “16-nm"
No full textNegli ultimi 30 anni, la legge di Moore è stata una linea guida per l'industria dei semiconduttori. Per sostenere la legge di Moore è richiesto un continuo scaling dei MOSFET in Si. Il corrente nodo tecnologico è di 22-nm, e le fasi successive previste dalla International Technology Roadmap for Semiconductor (ITRS) sono 16 nm e 11 nm. Questa tabella di marcia non garantisce che il CMOS basato su scaling del Si si estenderà ulteriormente e sta diventando sempre più pressante individuare una nuova famiglia di materiali a semiconduttore o di dispositivi in grado di sostenere la legge di Moore per alcune generazioni supplementari. I candidati più studiati sono materiali III-V, nanotubi, elettronica molecolare, spin-based computing, e dispositivi a singolo elettrone.
Tuttavia, molti di questi dispositivi sono allo stato di prototipo. Mentre i III-V FET e, in particolare, i transistor ad alta mobilità elettronica (HEMT) in InAIAs/InGaAs rappresentano una tecnologia già funzionante e la tecnologia produttiva per MOSHEMT in InGaAs è relativamente matura.
La mia attività di ricerca si è svolta in collaborazione con SEMATECH (USA), che ha fornito i dispositivi investigati. L’attività si è inizialmente concentrata su di MOSFET con canale in InGaAs, ZrO2 come dielettrico di gate e regioni di source/drain impiantate. E’ stato analizzato l'impatto delle trappole interfacciali sulle caratteristiche elettriche come tensione di soglia, pendenza del sottosoglia e correnti on/off in due MOSFET, uno convenzionale e uno a canale sepolto. E' stata effettuata un'analisi dettagliata degli effetti delle trappole di natura accettore e donore, evidenziando il comportamento non banale associato alle trappole donori nel dispositivo a canale sepolto
Un altro campo di indagine è stato l'ottimizzazione dello stack epitassiale componente un quantum-well MOSFET con Al2O3 dielettrico di gate a canale sepolto in InGaAs. Canale sepolto e MOSFET senza impianto delle regioni source/drain sono soluzioni studiate come alternativa alle strutture MOSFET standard, poiché minimizzano la degradazione della mobilità del canale ed evitano lo scattering all’interfaccia high-k/dielettrico causato dai cicli termici per l'attivazione doping. Concentrazione/tipo di doping e spessore degli strati che formano il dispositivo svolgono un ruolo chiave nel funzionamento. Per mezzo di simulazione abbiamo valutato l'impatto di differenti spessori e doping con lo scopo di fornire linee guida per progettazione e ottimizzazione dei dispositivi futuri.
L'elevata mobilità è la ragione principale per cui semiconduttori III-V sono studiati, è di fondamentale importanza conoscere i limiti e gli errori che influenzano le tecniche sperimentali per l'estrazione della mobilità. In particolare ci siamo concentrati sulla tecnica di estrazione della mobilità detta split-CV, applicata a quantum-well MOSFET con canale in InGaAs e Al2O3 dielettrico di gate. Simulare il metodo sperimentale split-CV ha permesso di trovare e parzialmente correggere tutti gli errori possibili che interessano l’estrazione della mobilità.
Infine, mi sono concentrato sulla caratterizzazione ed estrazione delle trappole di interfaccia in strutture III-V/high-k e Si/SiO2/high-k. Ho sviluppato una nuova tecnica generalizzata per l'estrazione delle trappole di interfaccia basata sulla combinazione di due metodi ben noti: il metodo Terman e il metodo high-low frequency. Ho applicato tale tecnica per la caratterizzazione delle trappole interfacciali in MOSFET a canale InGaAs con Al2O3 dielettrico di gate.
Invece, per studiare le trappole di interfaccia in strutture Si/SiO2/high-k abbiamo usato le tecniche di charge pumping e di “Trap Spectroscopy by Charge Injection and Sensing”. Infine, i parametri delle trappole estratti con i metodi sopra elencati sono stati confrontati con i parametri ottenuti tramite simulazioni in grado di riprodurre le correnti di perdita attraverso l'ossido di gate.For the last 30 years, Moore’s law has been a guiding principle for the semiconductor industry. To sustain the Moore’s law a continuous scaling of Si MOSFETs is required. The current technological node is 22-nm, and next steps foreseen by the International Technology Roadmap for Semiconductor (ITRS) are 16-nm and 11-nm. However, this roadmap does not guarantee that Si-based CMOS scaling will extend that far. Within this scenario, identifying a new semiconductor logic device technology that can sustain Moore’s law for a few additional generations is becoming increasingly pressing. Often mentioned candidates are III-V materials, nanotubes/nanowires, molecular electronics, spin-based computing, and single-electron devices.
However, at this time, many of these device concepts are hardly beyond the prototyping stage. In contrast, III-V FETs and, in particular, InAlAs/InGaAs high-electron mobility transistors (HEMTs) constitute a real device technology and InGaAs MOSHEMT manufacturing technology is relatively mature.
During my research activity I have collaborated with SEMATECH (USA), which provided the sample investigated. My activity has initially been concerned with MOSFETs with InGaAs channel, ZrO2 gate dielectric, and implanted source/drain regions. The impact of interfacial traps on the electrical characteristics such as threshold voltage, subthreshold slope and on/off currents has in particular been analyzed in both standard MOSFETs and capped MOSFETs. A detailed analysis of the effects of both acceptor and donor traps has been carried out, together with the explanation of the non-trivial behaviour induced by donor-like interface traps in capped MOSFETs.
Another field of investigation has been the optimization of the epilayer semiconductor stack composing buried-channel, InGaAs quantum-well MOSFETs with Al2O3 gate dielectric. Buried channel, implant-free MOSFETs are an option currently being intensively developed as an alternative to standard MOSFET structures, minimizing the channel mobility degradation induced by surface scattering and avoiding high-k dielectric degradation due to thermal cycles required for doping activation. Both doping concentration/type and thicknesses of the layers forming the buried channel device play a key role in the device performance. By means of numerical device simulations I have evaluated the impact of different device concepts to provide guidelines for device design and optimization.
Since the high mobility is the main reason why III-V semiconductor are being studied for Si replacement in the channel of next generation CMOS devices, it is of fundamental importance to asses the accuracy limits that affect the experimental techniques for mobility extraction. In particular we focused on the accuracy of split-CV measurements applied to quantum-well MOSFETs with InGaAs channel and Al2O3 gate dielectric. Simulating the split-CV experimental method has made it possible to find and partially correct all possible errors (interfacial traps, contact resistances and extra capacitance term associated with buried channel) affecting mobility extraction.
Finally, I focused on the interface-trap characterization and extraction at the III-V/high-k interface and Si/SiO2/high-k interface. I developed a new generalized technique for interface trap extraction in III-V devices. The technique is based on combining together two well known methods: the Terman method and the high-low frequency method. I applied the method to interface-trap characterization in InGaAs MOSFETs with Al2O3 gate dielectric.
On the other hand, charge pumping and “Trap Spectroscopy by Charge Injection and Sensing” techniques have been adopted to extract trap parameters in Si/SiO2/high-k interfaces. Results have been compared with trap parameters derived from current leakage simulations matching experimental data
Extraction of interface state density in oxide/III-V gate stacks
No full textExtracted interface trap densities (Dit) in the oxide/III-V gate stacks vary strongly with the utilized measurement procedures and values of device parameters used in the extraction analysis. Such Dit dependency on both selected procedures and parameters compromises unambiguous extraction of energy distributions of defects affecting device characteristics. To overcome this uncertainty, we propose an extraction approach, which combines the essential features of the high-low method and Terman method, allowing us to self-consistently determine Dit distribution along with values of the critical device parameters, effective oxide thickness (EOT) and substrate doping density (Nd)
Errors affecting split-CV mobility measurements in InGaAs MOS-HEMTs
No full textThe accuracy of the split-CV mobility extraction method is analyzed in implant-free, buried-channel InGaAs MOS-HEMTs with Al2O3 gate dielectric through a “simulated experiment” procedure. The different error sources affecting the method accuracy are pointed out. As a result of these errors, the split-CV mobility can appreciably underestimate the actual channel mobility under on-state conditions
Errors Limiting Split-CV Mobility Extraction Accuracy in Buried-Channel InGaAs MOSFETs
No full textThe accuracy of the split-CV mobility extraction method is analyzed in buried-channel InGaAs MOSFETs with Al2O3 gate dielectric and InP barrier, through a “simulated experiment” procedure using two-dimensional numerical device simulations preliminarily calibrated against experimental IV and CV curves. The different error sources limiting the method accuracy are pointed out. It is suggested that, as a result of these errors, the split-CV method can appreciably underestimate the actual channel mobility in these devices, with an error >20% and >50% on peak and high-VGS mobility, respectively. The method should therefore not be adopted for accurate mobility measurement in this operating regime, but only as a fast response technique providing a conservative estimation of channel mobility. Moreover, the method provides mobility values that rapidly drop below the peak value for decreasing VGS. It is shown that this behavior can be an artifact of the extraction method, that may mask physical mechanisms causing real mobility drop with decreasing channel carrier density like Coulomb scattering mechanisms. This poses limitations to the adoption of split-CV mobility as a reference for mobility model assessment in this operating regime. The proposed methodology can be applied to other III-V field-effect transistors, including both heterostructure-based and inversion-mode devices
Study of the Impact of Interface Traps on the Electrical Characteristics of InGaAs-based MOSFETs and MOSHEMTs with high-k Gate Dielectrics
No full textIn this paper, we use 2D numerical device simulations [Sentaurus Device, Synopsys Inc.] to investigate the impact of interface traps on the electrical characteristics of MOSFETs and MOSHEMTs with InGaAs channel and high-k gate dielectrics. More specifically, the following two technologies are taken into consideration: A) self-aligned inversion-type InGaAs/ZrO2 MOSFETs; B) implant-free InGaAs/Al2O3 MOSHEMTs
Advanced high-k materials and electrical analysis for memories: the role of SiO2-high-k dielectric intermixing
No full textThis paper presents an original approach for material studies for memory devices where the degree of intermixing between the high-k and interfacial SiO2 is explicitly quantified experimentally. Using calibrated leakage simulation the importance of intermixing is verified independently together with the conduction mechanism. The implication for NVM reliability are profound and will be discussed toward retention mechanisms and used to optimize retention margins for NVM memories
Engineering Barrier and Buffer Layers in InGaAs Quantum-Well MOSFETs
No full textProperties of InGaAs buried-channel quantum-well MOSFETs affected by the barrier and buffer layers are analyzed by numerical simulations to assist device engineering and optimization. The interplay between the charge-neutrality level position at the barrier/dielectric interface and conduction band discontinuity at the barrier/channel interface is shown to critically impact the achievement of an enhancement-mode device with full turn-on. A p-doped buffer is found to be a more suitable option than the standard unintentionally doped buffers to control short-channel effects
Going Beyond Counting First Authors in Author Co-citation Analysis
Full text linkThe present study examines one of the fundamental aspects of author co-citation analysis (ACA) - the way co-citation
counts are defined. Co-citation counting provides the data on which all subsequent statistical analyses and mappings
are based, and we compare ACA results based on two different types of co-citation counting - the traditional type that
only counts the first one among a cited work's authors on the one hand and a non-traditional type that takes into
account the first 5 authors of a cited work on the other hand. Results indicate that the picture produced through this non-traditional author co-citation counting contains more coherent author groups and is therefore considerably clearer. However, this picture represents fewer specialties in the research field being studied than that produced through the traditional first-author co-citation counting when the same number of top-ranked authors is selected and analyzed. Reasons for these effects are discussed
Variations on the Author
Full text link“Variations on the Author” discusses two of Eduardo Coutinho’s recent films (Um Dia na Vida, from 2010, and Últimas Conversas, posthumously released in 2015) and their contribution to the general question of documentary authorship. The director’s filmography is characterized by a consistent yet self-effacing form of authorial self-inscription: Coutinho often features as an interviewer that rather than express opinions propels discourses; an interviewer that is good at listening. This mode of self-inscription characterizes him as an author who is not expressive but who is nonetheless markedly present on the screen. In Um Dia na Vida, however, Coutinho is completely absent form the image, while Últimas Conversas, on the contrary, includes a confessional prologue that moves the director from the margins to the center of his films. This article examines the ways in which these works stand out in the filmography of a director who offers new insights into the notion of cinematic authorship
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