1,720,991 research outputs found
Flexible Precision Vector Extension for Energy Efficient Coarse-Grained Reconfigurable Array AI-Engine
No full textThe rapid development of Artificial Intelligence (AI) algorithms has created a need for a resource-optimised hardware accelerator. Among various platforms, Coarse-Grained Reconfigurable Array (CGRA) have gained importance as on-edge accelerators. They comprise of heterogeneous Processing Element (PE) matrix, which allows for high flexibility and parallelisation of calculations. They are mainly used for speeding up Data Flow Graph (DFG) execution. We aim to provide a general purpose, highly parameterised, and flexible architecture for AI on-edge data crunching. We propose a CGRA with a vector extension which allows for dynamically adjustable precision of calculation while maintaining a desired performance-power-area optimisation. It targets 4 bits integer (INT4) and 8 bits integer (INT8) quantization for fast and efficient Neural Network (NN) processing. In this paper, we examined hardware costs required to support the vector extension functionality. We synthesised the design on the 40nm Standard-Cell technology from TSMC. The obtained results show that the proposed extension attains on average 28.2% decrease in power consumption and 21.6% decrease in area compared to a reference design of the same computation power
Exploring Key Aspects of Soft GPGPU Computing for On-board Acceleration of Artificial Intelligence Algorithms in Space Applications
No full textArtificial Intelligence has gained widespread adoption across different industrial sectors, serving as a versatile tool to carry out a diverse array of tasks, ranging from image classification and traffic forecasting to natural language processing and speech recognition. In the space domain, however, a special focus must be placed on area overhead, power consumption, and fault-tolerant solutions. In this particular scenario, soft General-Purpose Computing on Graphic Processing Units has the potential to revolutionise space-related activities. Indeed, by leveraging both Field Programmable Gate Array technology and Graphic Processing Unit computing, it becomes feasible to achieve high-performance capabilities without compromising neither power consumption nor radiation tolerance features. Moreover, the use of reconfigurable hardware can facilitate the acceleration of a wide range of Machine Learning algorithms, avoiding the drawbacks of excessive specialisation. This paper explores the State-of-the-Art in terms of hardware platforms for on-the-edge acceleration of Artificial Intelligence algorithms and compares it with a possible System-on-Chip implementation based on a soft-Graphic Processing Unit. Then, the attention is shifted towards the investigation of key aspects for future space missions, such as reliability and Dynamic Partial Reconfiguration. We point out the lack of European technological solutions, emphasising the promising potential offered by NanoXplore devices. We also discuss the importance of fault detection and mitigation techniques in space applications, covering the most commonly employed hardware methods for reliability enhancement and highlighting the lack of work in the field of General-Purpose Computing for Graphic Processing Units, especially in the space sector. Furthermore, we briefly examine the implementation of Dynamic Partial Reconfiguration over a System-on-Chip featuring a soft-Graphic Processing Unit IP. Finally, in the last section of the paper, we hint at future development of the project and conclude the work
Extending the k-nearest-neighbor classification algorithm to symbolic objects
No full textL’analisi di dati simbolici generalizza alcuni metodi statistici standard al caso di oggetti simbolici (SO). Questi oggetti, informalmente definiti “dati aggregati”, poiché sintetizzano le informazioni relative ad un gruppo di individui, possono essere confrontati al fine di individuare dei cluster, di classificarli o ordinarli in base al loro grado di generalizzazione.
L’articolo propone un’estensione dell’algoritmo classico di classificazione K-Nearest Neighbor a tali oggetti. Il risultato di questo algoritmo è ancora un insieme di oggetti simbolici che possono essere studiati mediante altre tecniche di analisi di dati simbolici
Exploiting FPGA Dynamic Partial Reconfiguration for a Soft GPU-based System-on-Chip
No full textFor many years, General Purpose Computing on Graphic Processing Units has been widely exploited in different fields of application. The hardware architectures enabling this kind of computation are increasingly complex, and their use for on-the-edge applications is often constrained by the limited resources that characterise the systems involved. As such, implementing Graphic Processing Units as soft architectures on Field Programmable Gate Arrays could permit to tune their size, performance and resource usage accordingly to the application requirements. Exploiting the so-called Dynamic Partial Reconfiguration technology can allow specialisation of part of the system architecture, creating heterogeneous computing systems with better resource utilisation and lower power consumption. In this work, we describe the implementation on Field Programmable Gate Arrays of a System-on-Chip featuring a soft-Graphic Processing Unit, whose size and performance have been tuned by means of Partial Reconfiguration. Considering the Sobel Filter as a reference kernel, we discuss some results for reconfiguration time and throughput. Furthermore, we identify the minimum task sizes for which initiating the reconfiguration process gives an advantage in terms of execution time
Highly Parameterised CGRA Architecture for Design Space Exploration of Machine Learning Applications Onboard Satellites
No full textThe adoption of Machine Learning solutions directly onboard in satellite missions is becoming more and more attractive for the space sector. Among the various kinds of hardware accelerators, ranging from highly efficient yet inflexible COTS to more versatile FPGA-based solutions, Coarse-Grained Reconfigurable Array architectures are gaining importance in the field. CGRAs find applications in various domains, including digital signal processing, image and video processing, and cryptography, thus being considered also for space-related applications. They comprise an array of Processing Elements, whose complexity is between FPGA logic cells and general-purpose processors, interconnected through a Network on Chip. They excel in handling data-flow graphs and can be more efficient than FPGAs for the execution of specific tasks. Their versatility hinges on various architectural aspects of the coarse-grained array of Processing Elements. Among them, the supported operations, the possible interconnections, and the pipeline stages impact the functionality, the area, the power consumption, and the maximum frequency of the accelerator. In this work, we present a highly parameterised CGRA-based accelerator that we developed for an extensive Design Space Exploration on these architectures. The description starts from the CGRA building blocks, the Functional Units, and progresses towards the top level of the architecture, represented by the Node component, which is composed of an NxM matrix of Processing Elements. For each level of the hierarchy, we describe the HDL design parameters affecting the run-time reconfigurability of the accelerator, delving deeper into the functionality of the architecture. In the last section, we present synthesis results on the 40nm Standard-Cell technology from TSMC, highlighting performance, power consumption and area occupation for many different combinations of design parameters
Comparing dissimilarity measures for probabilistic symbolic objects
No full textSymbolic data analysis generalizes some standard statistical data mining methods, such as those developed for classification and clustering tasks, to the case of symbolic objects (SOs). These objects, informally defined as “aggregated data” because they synthesize information concerning a group of individuals of a population, ensure confidentiality of original data, nevertheless they pose new problems which finds a solution in symbolic data analysis. A by-product of working with aggregate data is the possibility of dealing with data from complex questionnaires, where multiple answers are possible or constraints among different answers exists. Comparing SOs is an important step of symbolic data analysis. It can be useful either to cluster some SOs or to discriminate between them, or even to order SOs according to their degree of generalization. This paper presents a comparative study aiming at evaluating the degree of dissimilarity between the objects of a restricted class of symbolic data, namely Probabilistic Symbolic Objects. To define a ground truth for the empirical evaluation, a data set with understandable and explainable properties has been selected. In the experiment, only two dissimilarity measures, among the seven ones we have studied, seems to have a more stable behaviour
Going Beyond Counting First Authors in Author Co-citation Analysis
Full text linkThe present study examines one of the fundamental aspects of author co-citation analysis (ACA) - the way co-citation
counts are defined. Co-citation counting provides the data on which all subsequent statistical analyses and mappings
are based, and we compare ACA results based on two different types of co-citation counting - the traditional type that
only counts the first one among a cited work's authors on the one hand and a non-traditional type that takes into
account the first 5 authors of a cited work on the other hand. Results indicate that the picture produced through this non-traditional author co-citation counting contains more coherent author groups and is therefore considerably clearer. However, this picture represents fewer specialties in the research field being studied than that produced through the traditional first-author co-citation counting when the same number of top-ranked authors is selected and analyzed. Reasons for these effects are discussed
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