1,721,005 research outputs found
A Class of Code Compression Schemes for Reducing Power Consumption in Embedded Microprocessor Systems
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Going Beyond Counting First Authors in Author Co-citation Analysis
Full text linkThe present study examines one of the fundamental aspects of author co-citation analysis (ACA) - the way co-citation
counts are defined. Co-citation counting provides the data on which all subsequent statistical analyses and mappings
are based, and we compare ACA results based on two different types of co-citation counting - the traditional type that
only counts the first one among a cited work's authors on the one hand and a non-traditional type that takes into
account the first 5 authors of a cited work on the other hand. Results indicate that the picture produced through this non-traditional author co-citation counting contains more coherent author groups and is therefore considerably clearer. However, this picture represents fewer specialties in the research field being studied than that produced through the traditional first-author co-citation counting when the same number of top-ranked authors is selected and analyzed. Reasons for these effects are discussed
Cervical myelography using a water-soluble contrast medium (metrizamide) injected laterally at C1-C2
No full textThe reliability of computerized axial tomography in the diagnosis of infratentorial mass lesions. A neurosurgical appraisal.
No full textA space-rated soft IP-core compatible with the PIC®hardware architecture and instruction set
No full textRadiation hardening for coping with cosmic-ray-induced faults in electronic equipment has always been a central topic of hardware/software development for aerospace missions. This work presents the design, verification and validation of an 8-bit space-rated RISC MCU FPGA soft-core, featuring hardware architecture and instruction set architecture full compliance with Microchip® PICmicro Midrange MCU. The MCU is code compatible with programs compiled with standard Microchip® tools and has been validated on a custom breadboard to qualify the design for the utilization in harsh space environment. The MCU features an 8-bit fault-tolerant processing core, two 8-bit GPIOs ports, an 8-bit SPI module, an 8-bit UART, a hard-coded non-maskable custom Watch-dog Timer (WDT), and an 8-bit Timer Module. Moreover, it provides two interrupt sources detecting faults inside the MCU Core. The development is compliant with standards ECSS-Q-ST-60-02C “Space product assurance: ASIC and FPGA development” and ECSS-Q-HB-60-02A “Space product assurance: Techniques for radiation effects mitigation in ASICs and FPGAs handbook”. The design features a selection of Radiation-Hardening-By-Design techniques to implement intrinsic and cost effective hardware fault-tolerance, namely Local Triple Modular Redundancy at register/gate level, Error Detection And Correction SEC-DED Hamming codes in memory cells, and Monostable WDT to reset the whole system after a detection of a Functional Interrupt. To emphasize application-tailored hardware cost, the program memory has been implemented in the FPGA LUT cells. The MCU has been synthesized on an Intel-Altera Cyclone IV FPGA device and a Microsemi RTAX-S 1000 rad-hard FPGA device. In both cases the maximum clock frequency is over 20 MHz, i.e. the original PICmicro frequency. An experimental test in artificially radiated operating environment is under development. The target applications for the MCU are low-cost program space missions based on CubeSat deployment. In particular, the on-board primary or secondary payload tasks, that are usually control and signal processing applications (e.g. technology demonstrator and university programs), can be implemented by the proposed fault-tolerant soft-IP core
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