1,721,046 research outputs found
Affidabilità e fisica dei guasti nei circuiti integrati in silicio
No full textL'affidabilità dei circuiti integrati riveste un'importanza crescente: ne vengono richiamati definizione e metodi di calcolo. Sono quindi esaminati i meccanismi di guasto principali, classificandoli secondo la localizzazione nella tessera di silicio
Elettromigrazione in dispositivi Emitter Coupled Logic con metallizzazioni in Al-Cu-Si
No full textThis paper summarizes results of accelerated testing on Emitter Coupled Logic bipolar integrated circuits. Electromigration effects on AlCuSi metallization and contacts are analyzed in detai
Investigation on ESD-stressed GaN/InGaN-on-sapphire blue LEDs
No full textAfter the results of a previous work [1], intermediate robustness of GaN/InGaN-on sapphire blue LEDs vs. ESD stress is
investigated. Different from other cases, no evidence for defect-related weakness is available. The role of resistive current paths
in focusing the flow of charge and the voltage peaks under both dc and transient conditions is then considered, by means of simple
considerations on a distributed network of elementary diodes and resistors representing the main electrical features of the LED
structure. EL and EBIC maps on both regular and failed devices support the proposed interpretatio
Measurement of the Local Latch-up Sensitivity By Means of Computer-controlled Scanning Electron-microscopy
No full textThe scanning electron microscopy (SEM) technique for the study of the local sensitivity to latch-up of CMOS integrated circuits is discussed. The technique is independent of a particular electric firing mechanism of latchup and does not require in-depth electrical characterization of the IC before the analysis. The electron beam in the SEM is adopted as a localized current injector, and the injected carriers are used to induce the latch-up state rather than to visualize its paths. A minicomputer-based system drives the beam position and automatically blanks the beam if the scan path has to cross areas which should be protected from charge injection. An example of application is described
Effects of high current and temperature in power MESFET metallization
No full textEffects of high current density and temperature closely combine to degrade power MESFETs during their operating life in radio-link systems. To understand failure mechanisms and distinguish between those accelerated by high current and/or by temperature, we have performed various dc tests and measured thermal resistance and thermal maps of tested devices
Potential of Digital Differential Voltage Contrast for the observation of latch-up phenomena in CMOS ICs.
No full textThe Digital Differential Voltage Contrast in a SEM has been applied to the observation of the latch-up phenomenon in CMOS ICs
The rule of the Rue Morgue: a decade later
No full textThe paper could limit itself to repeat the complaint that originated the first "Rules of the Rue Morgue", maybe updating the scenario of the many end users currently exposed to the risk of failed failure analyses. Nevertheless, some constructive proposals will be also pointed out, as those exposed by a recent paper (Cassanelli et al., 2005) that, dealing with the challenges in system reliability predictions, proposed some shortcuts to include even few field data into that process, and to include F.A. findings, when reliable, to skip cumbersome (and often not available) extraction of reliability parameters by statistical data. More specifically, in both the reported B and C cases the sudden occurrence of the failure mode was not related to any sudden firing of the root failure mechanisms, but other hidden roots have been identified, with completely different corrective actions with respect to the first interpretations. There is a simple and "correct" conclusion to this result: by means of thorough analyses, the first specimen (IGBT) was indicted for some higher sensitivity to latch-up, and the second (CMOS) to external EMI-induced ESD events. This could move to correct the corresponding pi factors employed for calculating the actual failure rate lambda drawing a physically sound shortcut to the estimation of the reliability parameters for some critical devices of a given electronic syste
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