18 research outputs found
Versatile surrogate models for IC buffers
No full textIn previous papers [1,2] the authors have investigated the use of Volterra series in the identification of IC buffer macro-models. While the approach benefited from some of the inherent qualities of Volterra series it preserved the two-state paradigm of earlier methods (see [3] and its references) and was thus limited in its versatility. In the current paper the authors tackle the challenge of going beyond an application or device-oriented approach and build versatile surrogate models that mimic the behavior of IC buffers over a wide frequency band and for a variety of loads thus achieving an unprecedented degree of generality. This requires the use of a more general system identification paradig
SOAs and Digital Linearization in Optical Networks-A Stochastic Investigation
No full textDigital predistortion has recently spurred interest in photonics. In this paper, the authors perform a sensitivity analysis of three digital predistortion algorithms and demonstrate an increase in performance and, in some cases, robustness to uncertainties
An Application of Volterra Series to IC Buffer Models
No full textInternational audienceThis paper presents a Volterra-based method of behavioral modeling for the I/O buffers of digital ICs. While this technique brings a slight improvement in accuracy over previous ones, its main strength is a greater degree of generality. With a modeling approach less dependent on the nature of the devices and more easily extendable to include the effects of multiple inputs one may hope better meet the challenges of advancing technology. The proposed models can be obtained from device port transient responses only and can be easily implemented in any simulation environment, including SPICE-based circuit description software. Two illustrative examples conclude the paper
A Fast Channel Simulation Framework Based on Hierarchical Waveform Representations
No full textInternational audienceWe present a modeling framework for high-speed coupled channels, which allows for the simulation of millions of bits in few seconds. The modeling approach extends the standard IBIS-AMI by including common-mode signals. Further, an expansion of the transient responses at both driver and receiver ports into hierarchical basis functions allows to easily represent long-term memory effects due to the possibly slow dynamics of pre-emphasis blocks. Numerical experiments demonstrate the high accuracy and efficiency of the proposed technique
Worst-Case Optimization of a Digital Link for Wearable Electronics in a Stochastic Framework
No full textInternational audienceThis paper demonstrates an optimization strategy for systems affected by uncertainties in the case of a textile interconnect line. Rather than simply conducting stochastic analysis at the end of the design process, tolerances are accounted for from the early stages of the flow. An unsupervised approach, used to describe the stochastic behavior of the line, is integrated within a heuristic optimization algorithm with the aim of selecting the optimal parameters of a passive equalizer
A simple algorithm for stable order reduction of z-domain Laguerre models
No full textInternational audienceDiscrete-time Laguerre series are a well known and efficient tool in system identification and modeling. This paper presents a simple solution for stable and accurate order reduction of systems described by a Laguerre model
Present and future of I/O-buffer behavioral macromodels
No full textSignal and Power Integrity (SI/PI) verification flows rely on accurate models for complex I/O-buffers that drive and receive electrical signals on high-speed channels. The sheer density of modern integrated circuits makes detailed transistor-level descriptions computationally cumbersome to the point where they become unusable for system level simulations. Fortunately, transistor-level descriptions may be replaced with more compact representations that approximate the input/output buffers behavior with considerable accuracy while providing a simulation speedup of several orders of magnitude. Known as behavioral models, surrogate models or macromodels, these computationally efficient equivalents have become a de-facto industry standard in SI/ PI simulations. This paper presents an overview of the state-of-the-art in I/O-buffer behavioral modeling, introducing the main features of both standard and emerging solutions. Open issues and future research directions are also discusse
Robust nonlinear models for CMOS buffers
No full textInternational audienceFor over a decade, buffer macromodeling has been a topic of great interest for the integrated circuit industry. The performance assessment of high-speed datalinks requires efficient means of simulating IC ports making compact and accurate behavioral models valuable instruments. In the present communication a new modeling technique, with several important advantages is described. The approach is purely “black-box”, relying exclusively on the observation of the external port voltages and currents safeguarding intellectual property. Unlike the standard algorithms currently used in EDA tools, the method described in this paper models the input-output behavior by means of a simple nonlinear system easy to identify and implement. Good model performance in overclocking conditions is an important advantage
