82 research outputs found
Operation of a large GEM-MSGC detector in a high intensity hadronic test beam using fully pipelined readout electronics
No full text98-060 In a recent test beam experiment at PSI a new tracking device for very high particle fluxes consisting of a low gain micro strip gas chamber (MSGC) combined with a gas electron multiplier (GEM) foil has been run under beam conditions similar to those foreseen in the HERA-B experiment [1], where such devices are being installed for the inner tracker. They are also being evaluated for the LHCb experiment [2]. In both detectors very high, mainly hadronic particle densities (up to 10 4 mm -2 sec -1) are expected, while the momentum resolution of the magnetic spectrometers foreseen in the two experiments is limited by multiple scattering. Also photon conversions represent a significant background source and therefore a minimal thickness in terms of radiation length is important, while position resolution requirements are moderate (typically 300 mu m pitch is sufficient). This paper describes the detailed construction of this novel detector, the test beam configuration and some of the data taken using the full HERA-B readout electronics
Proposal for the LHCb outer tracker front-end electronics
No full textA market survey on available TDCs for reading out the LHCb Outer Tracker has left over only one TDC, which is not optimal for this purpose. Hence, a new readout architecture which is based on a TDC to be developed anew has been defined. This system fits optimal the requirements of the LHCb Outer Tracker and also should be much cheaper. The system and its main issues are described in this paper
Design of a prototype frontend and bias generator for a new readout chip for LHCb
No full textThis paper presents the design and simulation results of components for a new LHCb readout chip for the silicon vertex detector, the inner tracking system, the pile-up veto trigger and the RICH. It is planned to use the same readout chip for these subdetectors. However, different versions of the analog input stages might be developed depending on the choice of the detector type.In section 1, the specification of the new readout chip named Beetle with respect to the different subdetector systems is described. Sections 2 and 3 describe the design and the simulation results of two test chips. The first chip contains different types of frontends for the vertex detector and the second chip bias generators. Section 4 gives a brief overview on the future plans for the development towards a readout chip for LHCb
HELIX128S-2—A readout chip for the silicon vertex detector and inner tracker detektor of HERA-B
No full textDesign of a prototype frontend and bias generator for a new readout chip for LHCb
No full textThis paper presents the design and simulation results of components for a new LHCb readout chip for the silicon vertex detector, the inner tracking system, the pile-up veto trigger and the RICH. It is planned to use the same readout chip for these subdetectors. However, different versions of the analog input stages might be developed depending on the choice of the detector type.In section 1, the specification of the new readout chip named Beetle with respect to the different subdetector systems is described. Sections 2 and 3 describe the design and the simulation results of two test chips. The first chip contains different types of frontends for the vertex detector and the second chip bias generators. Section 4 gives a brief overview on the future plans for the development towards a readout chip for LHCb
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