1,721,061 research outputs found
Symbolic Handling of Bridging Fault Effects
No full textThis paper introduces a new fault simulation methodology based onsymbolic handling of fault effects. Boolean variables are related tofaulty signals, and fault effects are propagated by computing gateoutput expressions by means of BDDs. The proposed technique canhandle in a single simulation step such faults as resistive bridges,that exhibit a parametric behavior, thus requiring more simulationswith conventional techniques
Applications of Boolean Satisfiability to Verification and Testing of Switch-Level Circuits
No full textThis work extends to the switch level the verification
and testing techniques based upon boolean satisfiability
(SAT), so that SAT-based methodologies can be applied
to circuits that cannot be well described at the gate level.
The main achieved goal was to define a boolean model
describing switch-level circuit operations as a SAT problem
instance, to be applied to combinational equivalence checking
and bridging-fault test generation. Results are provided
for a set of combinational CMOS circuits, showing the feasibility
of SAT-based verification and testing of switch-level
circuits
How Many Test Vectors We Need to Detect a Bridging Fault?
No full textThe growing dispersion of ICs’ parameters poses relevant uncertainties on gate output conductances and logic thresholds which play a main role in bridging fault detection. In this evolving context, the quality of fault simulation and test generation tools making use of nominal parameters should be verified. To analyze this problem we have studied bridging fault detection in combinational ICs in the presence of growing variations of IC’s parameters. Results show that a single test is not sufficient to ensure acceptable escape probabilities. Conversely, the minimal number of test vectors required to provide a null escape probability is upper bounded with respect to variations in the standard deviation of IC’s parameters. This result has been verified by means of Monte Carlo electrical level simulation. We propose a method to derive these minimal test sets in the case of low frequency tests. A fault simulator and a test generator have been developed supporting the search of minimal test sets targeting a null escape probability. These tools have been applied to a set of combinational benchmarks
A Novel Critical Path Heuristic for Fast Fault Grading
No full textThis work presents a new fault grading heuristic based on the critical path tracing technique that tackles the problems associated to fan-out reconverging nodes (FORN's) without using forward propagation of the fault effects. To determine the criticality status of a fanout reconverging node that can differ from that of its fan-out branches (FOB's), we use the concepts of evidencing and masking paths. Using the statistics from exact fault simulations, heuristic rules are derived for the generation of masking and evidencing paths. The results obtained on benchmark circuits show: a) good accuracy on fault coverage estimate; b) computation time linear in the number of gates and comparable to that of the fault-free simulation. © 1991 IEE
Dynamic Effects in the Detection of Bridging Faults in CMOS ICs
No full textDynamic effects in the detection of bridging faults in CMOS circuits are taken into account showing that a test vector designed to detect a bridging may be invalidated because of the increased propagation delay of the faulty signal. To overcome this problem, it is shown that a sequence of two test vectors , in which the second can detect a bridging fault as a steady error, can detect the fault independently of additional propagation delays if T0 initializes the faulty signal to a logic value different from the fault-free one produced by T1. This technique can be conveniently used both in test generation and fault simulation. In addition, it is shown how any fault simulator able to deal with FCMOS circuits can be modified to evaluate the impact of test invalidation on the fault coverage of bridging faults. For any test vector, this can be done by checking the state of the circuit produced by the previous test vector. © 1992 Kluwer Academic Publishers
Logiche di tipo BiCMOS
No full textIl lavoro presenta una panoramica dei principali aspetti relativi ai circuiti logici realizzati in tecnologia bipolare-CMOS (BiCMOS). In particolare, dopo una breve descrizione dei processi tecnologici, si discutono in qualche dettaglio i principali schemi elettrici utilizzati per la realizzazione dei gate. Inoltre, si introduce un modello analitico semplificato per il dimensionamento di massima dei circuiti, che è stato confrontato con i risultati di simulazioni circuitali
Going Beyond Counting First Authors in Author Co-citation Analysis
Full text linkThe present study examines one of the fundamental aspects of author co-citation analysis (ACA) - the way co-citation
counts are defined. Co-citation counting provides the data on which all subsequent statistical analyses and mappings
are based, and we compare ACA results based on two different types of co-citation counting - the traditional type that
only counts the first one among a cited work's authors on the one hand and a non-traditional type that takes into
account the first 5 authors of a cited work on the other hand. Results indicate that the picture produced through this non-traditional author co-citation counting contains more coherent author groups and is therefore considerably clearer. However, this picture represents fewer specialties in the research field being studied than that produced through the traditional first-author co-citation counting when the same number of top-ranked authors is selected and analyzed. Reasons for these effects are discussed
Novel Design for Testability Schemes for CMOS ICs
No full textThis work presents novel ideas to improve design for testability (DFT) of CMOS digital IC’s. In particular, two new techniques are suggested for non-stuck-at faults that avoid the drawbacks of previous solutions. Furthermore, an original method is proposed for on-line detection of delay faults, so far not yet considered in the context of DFT. All suggested schemes require limited extra hardware and minimal degradation of circuit performance. © 1990 IEE
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