188 research outputs found
Search for subsolar-mass black hole binaries in the second part of Advanced LIGO's and Advanced Virgo's third observing run
No full textWe describe a search for gravitational waves from compact binaries with at least one component with mass 0.2-1.0 M-circle dot and mass ratio q >= 0.1 in Advanced Laser Interferometer Gravitational-Wave Observatory (LIGO) and Advanced Virgo data collected between 2019 November 1, 15:00 UTC and 2020 March 27, 17:00 UTC. No signals were detected. The most significant candidate has a false alarm rate of 0.2 yr(-1). We estimate the sensitivity of our search over the entirety of Advanced LIGO's and Advanced Virgo's third observing run, and present the most stringent limits to date on the merger rate of binary black holes with at least one subsolar-mass component. We use the upper limits to constrain two fiducial scenarios that could produce subsolar-mass black holes: primordial black holes (PBH) and a model of dissipative dark matter. The PBH model uses recent prescriptions for the merger rate of PBH binaries that include a rate suppression factor to effectively account for PBH early binary disruptions. If the PBHs are monochromatically distributed, we can exclude a dark matter fraction in PBHs f(PBH) greater than or similar to 0.6 (at 90 per cent confidence) in the probed subsolar-mass range. However, if we allow for broad PBH mass distributions, we are unable to rule out f(PBH) = 1. For the dissipative model, where the dark matter has chemistry that allows a small fraction to cool and collapse into black holes, we find an upper bound f(DBH) < 10(-5) on the fraction of atomic dark matter collapsed into black holes
The Gigafitter: an Online Track Fitting Processor for CDF Experiment and Beyond
No full textReal time event reconstruction plays a fundamental role in High Energy Physics experiments. The CDF experiment at the Tevatron collider performs a fast online reconstruction of high-resolution tracks using the Silicon Vertex Trigger (SVT). We will describe the architecture, the performance and the impact on CDF physics program of a next generation online track fitter, the GigaFitter, developed to improve the SVT track reconstruction efficiency as the Tevatron instantaneous luminosity increases. The core of the GigaFitter is implemented in a modern Xilinx Virtex-5 FPGA chip, rich in powerful DSP arrays. The higher computation power allows to perform many tasks in parallel, reducing the track parameter reconstruction to a few clock cycles: as a result, the GigaFitter can perform more than one fit per nanosecond. The Gigafitter installation and commissioning were successfully completed in February 2010: 12 Track Fitter boards, one per each azimuthal sector of the silicon detector, have been replaced by a single Gigafitter board receiving the data from the entire tracking detector. Besides being much more compact and robust than the previous system, the Gigafitter increases the SVT track reconstruction efficiency and acceptance and copes more effectively with the high-occupancy events that occur frequently at the high luminosities the Tevatron currently delivers. Moreover, its architecture is general enough to be adapted to different experimental environments: the experience gained with the Gigafitter upgrade will be essential for future SVT-like tracking processor such as FTK at Atlas experiment
The GigaFitter: A next generation track fitter to enhance online tracking performances at CDF2009 IEEE Nuclear Science Symposium Conference Record (NSS/MIC)
No full textThe Silicon-Vertex-Trigger (SVT) is a processor developed at CDF experiment to perform online fast and precise track reconstruction. SVT is made of two pipelined processors: the Associative Memory finds low precision tracks looking for coincidences between hits from the tracking detectors and track candidates (roads) stored in memory; the Track Fitter refines the track quality whith high precision fits. The GigaFitter is a next generation track fitter, developed to reduce the degradation of the SVT efficiency due to the increasing instantaneous luminosity. It reduces the track parameter reconstruction to a few clock cycles and can perform many fits in parallel, thus allowing high resolution tracking at very high rate. The core of the GigaFitter is implemented in a modern Xilinx Virtex-5 FPGA chip, rich of powerful DSP arrays. With respect to the current Track Fitter, the GigaFitter is faster and provided of much more memory to store a greater number of roads to be used in the fit; this results in an increased SVT efficiency as more track candidates can be reconstructed. The GigaFitter has been installed in parasitic mode at CDF and has been tested against the current Track Fitter. We will describe the GigaFitter architecture, the parasitic installation at CDF and the performances with respect to the current system
The Gigafitter: An online track fitting processor for CDF experiment and beyondIEEE Nuclear Science Symposuim & Medical Imaging Conference
No full textReal time event reconstruction plays a fundamental role in High Energy Physics experiments. The CDF experiment at the Tevatron collider performs a fast online reconstruction of high-resolution tracks using the Silicon Vertex Trigger (SVT). We will describe the architecture, the performance and the impact on CDF physics program of a next generation online track fitter, the GigaFitter, developed to improve the SVT track reconstruction efficiency as the Tevatron instantaneous luminosity increases. The core of the GigaFitter is implemented in a modern Xilinx Virtex-5 FPGA chip, rich in powerful DSP arrays. The higher computation power allows to perform many tasks in parallel, reducing the track parameter reconstruction to a few clock cycles: as a result, the GigaFitter can perform more than one fit per nanosecond. The Gigafitter installation and commissioning were successfully completed in February 2010: 12 Track Fitter boards, one per each azimuthal sector of the silicon detector, have been replaced by a single Gigafitter board receiving the data from the entire tracking detector. Besides being much more compact and robust than the previous system, the Gigafitter increases the SVT track reconstruction efficiency and acceptance and copes more effectively with the high-occupancy events that occur frequently at the high luminosities the Tevatron currently delivers. Moreover, its architecture is general enough to be adapted to different experimental environments: the experience gained with the Gigafitter upgrade will be essential for future SVT-like tracking processor such as FTK at Atlas experiment
Development and Testing of the FDM Read-Out of the TES Arrays Aboard the LSPE/SWIPE Balloon-Borne Experiment
No full textThe design and experimental demonstration of a 16-channel frequency-domain multiplexing (FDM) read-out for transition-edge sensor bolometers is presented. This MUX electronics is intended to read out the 326 spiderweb bolometers of the LSPE/SWIPE balloon-borne experiment, which aims at the detection of the B mode polarization of the cosmic microwave background at large angular scales. The cryogenic part of our 16-channel FDM read-out chain features LC resonators composed of custom Nb superconducting inductors and surface mount device ceramic capacitors mounted on boards next to the detector wafers, at 300 mK, while the superconducting quantum interference device board is at 1.6 K. The warm section is based on a modular solution, with mezzanine plug-ins for digital-to-analog converters, analog-to-digital converters and a system-on-chip (based on the Altera Cyclone V field programmable gate array). The warm electronics handles the generation of the FDM tones, the de-multiplexing and the digital signal analysis including, e.g. cosmic ray glitches removal. Here, we recall its specifications, we address noise considerations, and finally we present the latest results obtained using flight models of our custom-designed boards
A frequency domain multiplexing system to readout the TES bolometers on the LSPE/SWIPE experiment
No full textLSPE/SWIPE is a balloon-borne experiment aimed at measuring the B-mode polarization of the cosmic microwave background (CMB) exploiting the reionization peak at l<10, with the primary target of improving the tensor-to-scalar ratio limit down to r=0.03 at 99.7% confidence level. SWIPE will use 326 spider-web Ti/Au transition-edge sensor (TES) bolometers, realized at INFN Genova, hosted on two focal planes cooled down at 300 mK and readout by superconducting quantum interference devices (SQUIDs), with multi-mode horns to couple the instrument's optical stages to the detectors. We present our design and demonstration of a 16-channel frequency domain multiplexing (FDM) system to readout SWIPE's TES bolometers
The FDM readout for the LSPE/SWIPE TES bolometers
No full textWe present the design and experimental demonstration of a 16-channel frequency domain multiplexing (FDM) readout for transition-edge sensor (TES) bolometers. This readout system is going to be implemented on the LSPE/SWIPE balloon-borne experiment, whose goal is to detect the polarization of cosmic microwave background (CMB) at large angular scales and whose launch is scheduled for December 2019. We describe the fabrication process of the Niobium superconducting inductors and the qualification tests performed in our 300 mK cryogenic facility in INFN Pisa of the boomerang shaped PCBs hosting the LC chains and the gradiometric SQUIDs, which are going to be mounted on the back of the SWIPE focal planes. The development of the warm readout electronics is presented, together with the firmware for the generation and readout of the biasing frequency comb
The AMchip04 and the Processing Unit Prototype for the FastTracker
No full textModern experiments search for extremely rare processes hidden in much larger background levels. As the experiment complexity and the accelerator backgrounds and luminosity increase we need increasingly complex and exclusive selections. We present the first prototype of a new Processing Unit, the core of the FastTracker processor for Atlas, whose computing power is such that a couple of hundreds of them will be able to reconstruct all the tracks with transverse momentum above 1 GeV in the ATLAS events up to Phase II instantaneous luminosities (5×1034 cm-2 s-1) with an event input rate of 100 kHz and a latency below hundreds of microseconds. We plan extremely powerful, very compact and low consumption units for the far future, essential to increase efficiency and purity of the Level 2 selected samples through the intensive use of tracking. This strategy requires massive computing power to minimize the online execution time of complex tracking algorithms. The time consuming pattern recognition problem, generally referred to as the “combinatorial challenge”, is beat by the Associative Memory (AM) technology [2] exploiting parallelism to the maximum level: it compares the event to pre-calculated “expectations” or “patterns” (pattern matching) at once looking for candidate tracks called “roads”. This approach reduces to linear the typical exponential complexity of the CPU based algorithms. The problem is solved by the time data are loaded into the AM devices. We describe the board prototypes that face the very challenging aspects of the Processing Unit: a huge amount of detector clusters (“hits”) must be distributed at high rate with very large fan-out to all patterns (10 Millions of patterns will be located on 128 chips placed on a single board) and a huge amount of roads must be collected and sent back to the FTK post-pattern-recognition functions. The Processing Unit consists of a 9U VME board, the AMBoard, controlled by an AUX card on the back of the crate. The AMBoard has a modular structure consisting of 4 mezzanines, the Local Associative Memory Banks (LAMB). Each LAMB contains 32 Associative Memory (AM) chips, 16 per side. The proto - AUX card provides hits on 8 buses for a total of 12 Gbits/sec to the AMBoard through 12 high frequency serial links and will sink the found roads trough other 16 high frequency serial links (24 Gbits/sec). A special P3 connector allows the communication between the front and rear boards placed on the same VME slot. A custom board profile has been studied and simulated at the CAD to guarantee a perfect board-to-board closure of the P3 connector without a backplane support in that region. A network of high speed serial links characterize the bus distribution on the AMBoard. The hit buses are fed to the four LAMBs and distributed to the 32 AM chips on the LAMB, through fanout chips. The LAMB realization has represented a significant technological challenge, due to the high density of chips allocated on both sides, and to the use of advanced packages and high frequency serial links
Performance of the AMBFTK board for the FastTracker processor for the ATLAS detector upgrade
No full textModern experiments at hadron colliders search for extremely rare processes hidden in a very large background. As the experiment complexity and the accelerator backgrounds and luminosity increase we need increasingly complex and exclusive selections. The FastTracker (FTK) processor for the ATLAS experiment offers extremely powerful, very compact and low power consumption processing units for the future, which is essential for increased efficiency and purity in the Level 2 trigger selection through the intensive use of tracking. Pattern recognition is performed with Associative Memories (AM). The AMBFTK board and the AMchip04 integrated circuit have been designed specifically for this purpose. We report on the preliminary test results of the first prototypes of the AMBFTK board and of the AMchip04
GigaFitter: Performance at CDF and perspective for future applications
No full textThe Silicon Vertex Trigger (SVT) at CDF is made of two pipelined processors: the Associative Memory finding low precision tracks and the Track Fitter refining the track quality with high-precision fits. We will describe the performance of a next generation track fitter, the GigaFitter, that performs more than a fit per nanosecond. It is going to be inserted parasitically in SVT to study its capabilities to improve data taking during the high luminosity CDF runs. This device is based on modem FPGA technology, rich of powerful DSP arrays, to reduce the track parameter reconstruction to few clock cycles and perform many fits in parallel. The goal of the design was to reduce significantly the processing time required for fitting and thus allow more time for the subsequent high resolution track-fitting. Preliminary results on the algorithm latency are presented. A future more power-full version of the GigaFitter intended for WC experiments is also discusse
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