1,099 research outputs found
System-on-chip Computing and Interconnection Architectures for Telecommunications and Signal Processing
No full textThis dissertation proposes novel architectures and design techniques targeting SoC building blocks for telecommunications and signal processing applications.
Hardware implementation of Low-Density Parity-Check decoders is approached at both the algorithmic and the architecture level. Low-Density Parity-Check codes are a promising coding scheme for future communication standards due to their outstanding error correction performance.
This work proposes a methodology for analyzing effects of finite precision arithmetic on error correction performance and hardware complexity. The methodology is throughout employed for co-designing the decoder. First, a low-complexity check node based on the P-output decoding principle is designed and characterized on a CMOS standard-cells library. Results demonstrate implementation loss below 0.2 dB down to BER of 10^{-8} and a saving in complexity up to 59% with respect to other works in recent literature. High-throughput and low-latency issues are addressed with modified single-phase decoding schedules. A new "memory-aware" schedule is proposed requiring down to 20% of memory with respect to the traditional two-phase flooding decoding. Additionally, throughput is doubled and logic complexity reduced of 12%. These advantages are traded-off with error correction performance, thus making the solution attractive only for long codes, as those adopted in the DVB-S2 standard. The "layered decoding" principle is extended to those codes not specifically conceived for this technique. Proposed architectures exhibit complexity savings in the order of 40% for both area and power consumption figures, while implementation loss is smaller than 0.05 dB.
Most modern communication standards employ Orthogonal Frequency Division Multiplexing as part of their physical layer. The core of OFDM is the Fast Fourier Transform and its inverse in charge of symbols (de)modulation. Requirements on throughput and energy efficiency call for FFT hardware implementation, while ubiquity of FFT suggests the design of parametric, re-configurable and re-usable IP hardware macrocells. In this context, this thesis describes an FFT/IFFT core compiler particularly suited for implementation of OFDM communication systems. The tool employs an accuracy-driven configuration engine which automatically profiles the internal arithmetic and generates a core with minimum operands bit-width and thus minimum circuit complexity. The engine performs a closed-loop optimization over three different internal arithmetic models (fixed-point, block floating-point and convergent block floating-point) using the numerical accuracy budget given by the user as a reference point. The flexibility and re-usability of the proposed macrocell are illustrated through several case studies which encompass all current state-of-the-art OFDM communications standards (WLAN, WMAN, xDSL, DVB-T/H, DAB and UWB). Implementations results are presented for two deep sub-micron standard-cells libraries (65 and 90 nm) and commercially available FPGA devices. Compared with other FFT core compilers, the proposed environment produces macrocells with lower circuit complexity and same system level performance (throughput, transform size and numerical accuracy).
The final part of this dissertation focuses on the Network-on-Chip design paradigm whose goal is building scalable communication infrastructures connecting hundreds of core. A low-complexity link architecture for mesochronous on-chip communication is discussed. The link enables skew constraint looseness in the clock tree synthesis, frequency speed-up, power consumption reduction and faster back-end turnarounds. The proposed architecture reaches a maximum clock frequency of 1 GHz on 65 nm low-leakage CMOS standard-cells library. In a complex test case with a full-blown NoC infrastructure, the link overhead is only 3% of chip area and 0.5% of leakage power consumption.
Finally, a new methodology, named metacoding, is proposed. Metacoding generates correct-by-construction technology independent RTL codebases for NoC building blocks. The RTL coding phase is abstracted and modeled with an Object Oriented framework, integrated within a commercial tool for IP packaging (Synopsys CoreTools suite). Compared with traditional coding styles based on pre-processor directives, metacoding produces 65% smaller codebases and reduces the configurations to verify up to three orders of magnitude
Proceedings - 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools, DSD 2008
No full textEuromicro Symposium on Digital System design: Architectures, Methods and Tools (DSD) addresses the
key issues in design, architectures and implementation of digital systems. DSD is a discussion forum for
researchers and engineers working on architectures and implementations of (embedded) digital
systems, as well as efficient design methods and tools.
This year, DSD2008 hosted six Special Sessions, namely Special Session on “Fault Tolerance in Digital
System Design” organized by Zdenek Kotásek, Brno University of Technology (CZ), Special Session on
“Prospective aspects of Networks-on-Chip” organized by Claas Cornelius, University of Rostock (DE),
Special Session on “Dependability and Testing of Digital Systems” organized by Hana Kubátová, Czech
Technical University in Prague (CZ), Special Session on “Planning and Optimization of Sensor Network
Systems” organized by William Fornaciari, Politecnico Milano (IT), Special Session on “System-Level
Energy Optimization of Embedded Software” organized by Eugenio Villar, Universidad de Cantabria (ES)
and Special Session on “NEWCOM++: Flexible Radio Digital Design” organized by Dominique Noguet,
CEA-LETI (FR). I would like to thank the Special Session organizers and their respective program
committees for the time and effort they put in organizing the Special Sessions.
This year, DSD attracted 179 submissions from 37 countries around the world. The increased number of
submissions and wide geographical spread demonstrate the growing popularity of DSD and the
relevance of the topics covered. All submitted works underwent a stringent and blind review process
carried on by at least three independent referees. In some uncertain cases the number of referees was
up to four. Based on the referee reports, the Program Committee selected 46 papers for long
presentation, 46 papers for short presentation and 31 poster presentations.
The three keynote speeches are very topical and are presented by experts from leading semiconductor
and electronic design automation industries. I am sure all participants will enjoy and benefit from the
keynote presentations. A pre-conference Tutorial Day composed of two tutorials entitled: “Qualitydriven
model-based architecture synthesis for real-time embedded SoCs” and “Application mapping on
a composable multi-core NoC-based SoC platform CoMPSoC” are delivered by researchers from NXP
Semiconductors and Eindhoven University of Technology (The Netherlands).
It is a privilege and honor for me to be a chair of the DSD Program Committee. It has been a rewarding
experience. I would like to take this opportunity to thank all of those who worked hard to bring the
programme and the proceedings together. This includes all the Program Committee members and extra
reviewers. I sincerely thank them for their co-operation in the refereeing process. I would like to
express my thanks and gratitude to the Steering Committee members Lech Jozwiak, Antonio Nunez and
Krzysztof Kuchcinski for their constant support and advice. I would like to mention particularly the
unreserved help extended by Prof. Lech Jozwiak.
The symposium could not materialize without the organizing Committee headed by Gianni Conte and
Monica Mordonini (University of Parma) and by Gianni Danese and Francesco Leporati (University of
Pavia). Their hard work will be certainly fruitful to all the participants and will make the stay in Parma
a wonderful experience. My special thanks go to my colleague Sergio Saponara, who assisted me at
every step during the whole year. My thanks and appreciation goes to my Ph.D. Nicola Eugenio
L’Insalata who took care of DSD 2008 web pages.
Last but not least, I would like to thank all the authors for their interest in DSD. Thank you for your
time and effort in preparing and submitting your work to DSD and your patience through the long
process. Your hard work is the backbone of the conference.
I wish you all a pleasant and fruitful meeting in Parma
Motion estimation and CABAC VLSI co-processors for real-time high-quality H.264/AVC video coding
No full textReal-time and high-quality video coding is gaining a wide interest in the research and industrial community for different applications. H.264/AVC, a recent standard for high performance video coding, can be successfully exploited in several scenarios including digital video broadcasting, high-definition TV and DVD-based systems, which require to sustain up to tens of Mbits/s. To that purpose this paper proposes optimized architectures for H.264/AVC most critical tasks, Motion estimation and context adaptive binary arithmetic coding. Post synthesis results on sub-micron CMOS standard-cells technologies show that the proposed architectures can actually process in real-time 720 × 480 video sequences at 30 frames/s and grant more than 50 Mbits/s. The achieved circuit complexity and power consumption budgets are suitable for their integration in complex VLSI multimedia systems based either on AHB bus centric on-chip communication system or on novel Network-on-Chip (NoC) infrastructures for MPSoC (Multi-Processor System on Chip
Design of an ASIC for fast signal recognition and code acquisition in DS-SS-CDMA receivers
No full textThis paper deals with the design and realization of an Application Specific Integrated Circuit (ASIC) for fast Signal Recognition and Code Acquisition (SR/CA) in Direct-Sequence Spread-Spectrum Code Division Multiple Access (DS-SS-CDMA) receivers operating in a satellite or terrestrial radio network. The SR/CA problem is often the bottleneck of any DS-SS-CDMA system operating in spread-Aloha random access mode for the common access channel or when packet mode operation is envisaged. The single ASIC implementation provides a reliable, high-performance, low-cost, low-power consumption solution to such a problem. In particular, this paper explains how a parallel acquisition circuit can be effectively implemented on a single chip with a 1.0 μm CMOS (Complementary Metal Oxide Silicon) technology, complying with the specifications of the ESA (European Space Agency)/Inisel Ku-band CDMA VSAT (Very Small Aperture Terminal) system
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