69 research outputs found
Creation of web pages with semantic markups for a research group
No full textIt is the age of web 3.0 now. The Semantic Web is being built by converting web content into machine-readable data, so it is also called "web of data". The main approach for this goal is to describe the web pages with semantic markups. The markups apply terms from certain vocabularies in a specialized format for corresponding content. They are written in the web page documents. And when the search engines read these documents, the markups are detected to help to match better results to users’ searches. In this project, new responsive web page templates are designed for a research group of UPM. The responsive feature means that the pages can be displayed properly in different devices with diverse screen sizes. And then these templates are marked up to produce machine-readable data. The markup method used is RDFa and the vocabulary applied is Schema.org vocabulary. The code of each template has to pass the test using a structured data testing tool developed by Google to ensure that the markups work without errors. The templates made in the project will be used for future development of more pages when the website of the research group is really implemented
Virtual Blue Noise Lighting
No full textWe introduce virtual blue noise lighting, a rendering pipeline for estimating indirect illumination with a blue noise distribution of virtual lights. Our pipeline is designed for virtual lights with non-uniform emission profiles that are more expensive to store, but required for properly and efficiently handling specular transport.
Unlike the typical virtual light placement approaches that traverse light paths from the original light sources, we generate them starting from the camera. This avoids two important problems: wasted memory and computation with fully-occluded virtual lights, and excessive virtual light density around high-probability light paths. In addition, we introduce a parallel and adaptive sample elimination strategy to achieve a blue noise distribution of virtual lights with varying density. This addresses the third problem of virtual light placement by ensuring that they are not placed too close to each other, providing better coverage of the (indirectly) visible surfaces and further improving the quality of the final lighting estimation.
For computing the virtual light emission profiles, we present a photon splitting technique that allows efficiently using a large number of photons, as it does not require storing them. During lighting estimation, our method allows using both global power-based and local BSDF important sampling techniques, combined via multiple importance sampling. In addition, we present an adaptive path extension method that avoids sampling nearby virtual lights for reducing the estimation error.
We show that our method significantly outperforms path tracing and prior work in virtual lights in terms of both performance and image quality, producing a fast but biased estimate of global illumination.</jats:p
Automatic GPU Data Compression and Address Swizzling for CPUs via Modified Virtual Address Translation
No full textCompacted CPU/GPU Data Compression via Modified Virtual Address Translation
No full textWe propose a method to reduce the footprint of compressed data by using modified virtual address translation to permit random access to the data. This extends our prior work on using page translation to perform automatic decompression and deswizzling upon accesses to fixed rate lossy or lossless compressed data. Our compaction method allows a virtual address space the size of the uncompressed data to be used to efficiently access variable-size blocks of compressed data. Compression and decompression take place between the first and second level caches, which allows fast access to uncompressed data in the first level cache and provides data compaction at all other levels of the memory hierarchy. This improves performance and reduces power relative to compressed but uncompacted data. An important property of our method is that compression, decompression, and reallocation are automatically managed by the new hardware without operating system intervention and without storing compression data in the page tables. As a result, although some changes are required in the page manager, it does not need to know the specific compression algorithm and can use a single memory allocation unit size. We tested our method with two sample CPU algorithms. When performing depth buffer occlusion tests, our method reduces the memory footprint by 3.1x. When rendering into textures, our method reduces the footprint by 1.69x before rendering and 1.63x after. In both cases, the power and cycle time are better than for uncompacted compressed data, and significantly better than for accessing uncompressed data.Proceedings of the ACM on Computer Graphics and Interactive TechniquesHardware Architectures and Space Partitioning3
Hardware Adaptive High-Order Interpolation for Real-Time Graphics
No full textInterpolation is a core operation that has widespread use in computer graphics. Though higher-order interpolation provides better quality, linear interpolation is often preferred due to its simplicity, performance, and hardware support. We present a unified refactoring of quadratic and cubic interpolations as standard linear interpolation plus linear interpolations of higher-order terms and show how they can be applied to regular grids and (triangular/tetrahedral) simplexes Our formulations can provide significant reduction in computation cost, as compared to typical higher-order interpolations and prior approaches that utilize existing hardware linear interpolation support to achieve higher-order interpolation. In addition, our formulation allows approximating the results by dynamically skipping some higher order terms with low weights for further savings in both computation and storage. Thus, higher-order interpolation can be performed adaptively, as needed. We also describe how relatively minor modifications to existing GPU hardware could provide hardware support for quadratic and cubic interpolations using our approach for both texture filtering operations and barycentric interpolation. We present a variety of examples using triangular, rectangular, tetrahedral, and cuboidal interpolations, showing the effectiveness of our higher-order interpolations in different applications.Computer Graphics ForumHigh-Performance Rendering40
Poly[octaaquadi-μ-phosphato-trinickel(II)]. Corrigendum
No full textA correction is made to the name of the first author in Shouwen, Wang, Gao, Wen & Zhou [Acta Cryst. (2008), E64, m259]
An inquiry into AI university curriculum and market demand: Facts, fits, and future trends
No full text© 2019 Copyright is held by the owner/author(s). This study aims at exploring the fit/misfit between artificial intelligence (AI) curriculum objectives and AI-relevant job qualifications. In our preliminary analysis, we applied the data collected from a major employment website and multiple university programs to extricate dimensions and properties for academic curriculum design and job qualifications, respectively. After investigating AI career market demand and supply, we recommend aligning AI curriculum with current and future market demands. Envisioning our future research, further theoretical development with supportive evidence should be leveraged to interpret the fit/misfit between AI curriculum design and market needs
Dimension conversion and scaling of disordered protein chains
No full textTo extract protein dimension and energetics information from single-molecule fluorescence resonance energy transfer spectroscopy (smFRET) data, it is essential to establish the relationship between the distributions of the radius of gyration (R-g) and the end-to-end (donor-to-acceptor) distance (R-ee). Here, we performed a coarse-grained molecular dynamics simulation to obtain a conformational ensemble of denatured proteins and intrinsically disordered proteins. For any disordered chain with fixed length, there is an excellent linear correlation between the average values of R-g and R-ee under various solvent conditions, but the relationship deviates from the prediction of a Gaussian chain. A modified conversion formula was proposed to analyze smFRET data. The formula reduces the discrepancy between the results obtained from FRET and small-angle X-ray scattering (SAXS). The scaling law in a coil-globule transition process was examined where a significant finite-size effect was revealed, i.e., the scaling exponent may exceed the theoretical critical boundary [1/3, 3/5] and the prefactor changes notably during the transition. The Sanchez chain model was also tested and it was shown that the mean-field approximation works well for expanded chains.Ministry of Science and Technology of China [2015CB910300]SCI(E)[email protected]
Hardware-Accelerated Dual-Split Trees
No full textBounding volume hierarchies (BVH) are the most widely used acceleration structures for ray tracing due to their high construction and traversal performance. However, the bounding planes shared between parent and children bounding boxes is an inherent storage redundancy that limits further improvement in performance due to the memory cost of reading these redundant planes. Dual-split trees can create identical space partitioning as BVHs, but in a compact form using less memory by eliminating the redundancies of the BVH structure representation. This reduction in memory storage and data movement translates to faster ray traversal and better energy efficiency. Yet, the performance benefits of dual-split trees are undermined by the processing required to extract the necessary information from their compact representation. This involves bit manipulations and branching instructions which are inefficient in software. We introduce hardware acceleration for dual-split trees and show that the performance advantages over BVHs are emphasized in a hardware ray tracing context that can take advantage of such acceleration.We provide details on how the operations needed for decoding dual-split tree nodes can be implemented in hardware and present experiments in a number of scenes with different sizes using path tracing. In our experiments, we have observed up to 31% reduction in render time and 38% energy saving using dual-split trees as compared to binary BVHs representing identical space partitioning.Proceedings of the ACM on Computer Graphics and Interactive TechniquesHardware Architectures and Space Partitioning3
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