1,721,039 research outputs found
Multiplierless coprocessor for difference of Gaussian (DOG) calculation
No full textA hardware architecture is applied to the calculation of a Difference-of-Gaussian filter, which is typically employed in image processing algorithms. The architecture has a modular structure to easily allow the matching of the desired delay/area ratio as well as a high computational accuracy. A new solution is provided for the implementation of multiply-accumulators which allows a significant reduction of area with respect to the conventional architectures
An H.264 Encoder for Real Time Video Processing Designed for SPEAr Customizable System-on-Chip Family
No full textIn this paper an H.264/AVC baseline profile encoder is proposed, designed to be implemented on the STMicroelectronics SPEAr customizable SoC family. Computational intensive modules, like motion estimation and compensation, have been implemented in hardware and prototyped on a Xilinx FPGA where they operate at the maximum frequency of 56.179 MHz. To gain a good adaptiveness for different aims, the variable length coding and the assembly of the output bitstream run on the embedded ARM processor. The high speed obtained and PSNR values of about 35 dB show that the architecture proposed can be successful implemented on low-cost platform also for real time applications
Design of a context-adaptive variable length encoderfor real-time video compression on reconfigurable platforms
No full textIn this study, a new context-adaptive variable length-coding encoder architecture is proposed particularly aimed to be
implemented with field programmable logics (FPL) like FPGAs. The design implements different approaches in order to
minimise the area cost as well as to speed up the coding efficiency, which allows real-time compression of 1080 p video
streams coded in YCbCr 4:2:0 format. Priority cascading logics have been implemented in order to increase the parallelisation
degree of the pre-coding stage, thus favouring the limitation of the number of clock cycles needed for the extraction of
symbols from the input data, whereas the employment of the arithmetic table elimination technique has allowed a large-area
reduction of the encoder thanks to the elimination of 18 of the 38 tables needed for the encoding stage. The design achieves
real time elaboration with an operation frequency of 63 MHz and occupies 2200 look-up table (LUT)s when implemented on
a low-cost, low-end XILINX Spartan 3 FPGA, thus overcoming the most recent FPL implementation and making this
encoder quite comparable both in terms of area and speed with some recently proposed ASIC implementations, so that it
turns out to be a valid alternative also for application specific implementations
A Self-Consistent Model of the OCVD Behaviour of Si and 4H-SiC P+-N-N+ Diodes
No full textA comprehensive analytical model of the open-circuit voltage-decay (OCVD) response for a generic diode, switched from an arbitrary forward-bias condition, is proposed. To properly account for the steady-state conditions of the diode, the dynamic model incorporates an accurate description of the static I- V curves, which turns also useful for better understanding the influence of physical parameters on voltage transitory. As shown from comparisons with simulations and experiments, the model accurately describes the spatial-temporal variation of carriers and currents along the whole epilayer and allows one to resolve some ambiguities reported in the literature, such as the stated inapplicability of the OCVD method on thick epilayers, the reasons of the observed nonlinear decay of the voltage with time, and the effects of junction properties on voltage transient
High Speed CAVLC Encoder Suitable for Field Programmable Platforms
No full textIn this paper a new Context-Adaptive Variable-
Length Coding encoder is proposed particularly aimed to be
implemented with Field Programmable Logics. The design employs redundant circuitry to implement priority cascading logics which allows to highly improve its degree of parallelism,
while the area cost related to the unavoidable replication of
logic blocks has been balanced by means of arithmetic manipulations capable to eliminate some of the most area demanding tables of variable-length codewords. The proposed design is capable to process 1080p@30 HDTV video streams coded in YCbCr 4:2:0, when it is implemented with a low-cost, lowspeed FPGA
Modeling and Characterization of the OCVD Response at an Arbitrary Time and Injection Level
No full textWe show that the OCVD method can be improved by providing the test diode with a third terminal that enables the suppression of the ohmic drop effect on voltage decay measurements. It’s demonstrated that in this way the OCVD response can be extended up to the built-in voltage limit of the diode, where the carrier injection in the heavily doped regions and the Auger mechanism are dominating. Moreover, to physically interpret the numerical simulations, an analytical model has been developed which is capable to describe the voltage response as a continuous function of time and injection level
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