1,721,054 research outputs found
Electromigration Induces Stress: A study into current induced resistance changes in VLSI interconnects
No full textDielectric engineering: Characterization, development and process damage minimization of various silicon oxides
Get PDFOver the various chapters, this thesis describes the characterization and development of a number of applications of silicon dioxides. An oxynitride is developed allowing a much higher SiGe epitaxial deposition rate in a bipolar process. Also a tunneloxide for non volatile memory application is developed and characterized. Once the oxide has been formed and defined it is exposed to the sometimes harsh environments during the following processing steps. Possible process damage due to this exposure is characterized, evaluation methods are developed, process steps are engineered for damage reduction and protection methods are developed
Going Beyond Counting First Authors in Author Co-citation Analysis
Get PDFThe present study examines one of the fundamental aspects of author co-citation analysis (ACA) - the way co-citation
counts are defined. Co-citation counting provides the data on which all subsequent statistical analyses and mappings
are based, and we compare ACA results based on two different types of co-citation counting - the traditional type that
only counts the first one among a cited work's authors on the one hand and a non-traditional type that takes into
account the first 5 authors of a cited work on the other hand. Results indicate that the picture produced through this non-traditional author co-citation counting contains more coherent author groups and is therefore considerably clearer. However, this picture represents fewer specialties in the research field being studied than that produced through the traditional first-author co-citation counting when the same number of top-ranked authors is selected and analyzed. Reasons for these effects are discussed
Reliability engineering in RF CMOS
Get PDFIn this thesis new developments are presented for reliability engineering in RF CMOS. Given the increase in use of CMOS technology in applications for mobile communication, also the reliability of CMOS for such applications becomes increasingly important. When applied in these applications, CMOS is typically referred to as RF CMOS, where RF stands for radio frequencies
Detection of and protection against plasma charging damage in modern IC Technology
Get PDFPlasmas are key for enabling technologies in modern ultra-large scale integrated (ULSI) circuit manufacturing. Since the modern ULSI circuit consists of 107-108 transistors, the back-end-of-line (BEOL) metallization process with a multi-level interconnection of these transistors is a major technological challenge. These advanced multi-level interconnections can only be made by using high density plasma-enhanced deposition and etching techniques. However, a plasma is also a very harsh environment to integrated circuit (IC) products. A plasma could generate an unintended high electrical field which stresses and degrades the underlying thin gate oxide layer of the metal-oxide-silicon (MOS) transistors and non-volatile memories (NVM) as well as the insulator of MIM capacitors. MOS, NVM and MIM capacitors are major elements which form IC’s. Therefore the yield and reliability of these IC products are degraded by plasma charging damage. How to detect, control and reduce plasma charging damage becomes a formidable challenge in modern IC technology. In this thesis, the ways to detect and reduce plasma charging damage in the context of back-end-of-line (BEOL) processes have been studied
Full chip modelling of ICs under CDM stress
Get PDFIn this thesis, CDM ESD stress on the Integrated Circuits (IC) and the various factors which affect the robustness of an IC design against CDM stress is investigated. One of the main reasons for CDM failure are the voltage gradients set across the circuit during CDM stress. The IC being also the source, its discharge current path is not constrained near the input and output pads as in other kinds of ESD stress. Instead it can be anywhere through the internal circuitry into the ground. The major hinderance in developing a CDM robust protection design is the lack of knowledge on the CDM current and its discharge path through the circuit. CDM withstand level, is package dependent and it is impossible to characterize a circuit design to be CDM robust independent of its package type
Electrostatic discharge effects in thin film transistors
Get PDFAlthough amorphous silicon thin film transistors (α-Si:H TFT’s) have a very low electron mobility and pronounced instabilities of their electrical characteristics, they are still very useful and they have found their place in the semiconductors industry, as they possess some very good properties: they can be deposited under low temperature and over a large area, and they are very cheap. It is proved from practice that electrostatic discharge (ESD) is one of the most important issues in thin film electronics. It jeopardizes reliable operation of thin film transistors, firstly during the manufacturing process in the cleanroom, and also in some cases during their operation. Having a large on-resistance, α-Si:H TFT’s are very difficult from the point of ESD protection, as it is difficult to sink the current. Another difficulty for the ESD protection is that they are also built on an insulation substrate. Finally, the testing methods and the design rules that are already developed for the silicon integrated circuits are not applicable on the amorphous silicon TFT’s. Therefore an original design has to be created in order to protect TFT circuits from the electrostatic discharge
Electrical instability of a-Si:H/SiN thin film transistors: a study at room temperature and low voltage stress
Get PDFThe thesis shows the results of four years of research into the electrical stability of a-Si:H/SiN TFTs. Various methods of investigation of a-Si:H/SiN TFTs have been carried out in this thesis towards understanding the causes of degradation that shortens the transistor lifetime and narrows the transistor application area. The research aims to cast light on the mechanism responsible for a-Si:H/SiN TFTs degradation during short and long period of voltage stress at room temperature
Physics of Trap Generation and Electrical Breakdown in Ultra-thin SiO2 and SiON Gate Dielectric Materials
No full textThis work spans nearly a decade of industrial research in the reliability physics of deeply scaled SiO2 and SiON gate dielectrics. In this work, we will present our following original contributions to the field: • Below 5V stress, the dominant mechanism for stressed induced leakage current in the off-state is tunneling via interface traps in films less than 35Å thick. This finding enhances the value of SILC measurements as a probe of trap generation. LV-SILC is a two-trap process and senses interface states at both top and bottom interfaces. • A conclusive experimental proof of the IBM energy driven breakdown theory, showing that breakdown is indeed voltage rather than field driven in ultra-thin oxides. This work has been instrumental in ending the long running controversy in the industry on breakdown models. • Experimental verification of the Bell Labs theory that anode hole injection through minority ionization remains a plausible breakdown mechanism down to 3.6V. This finding shows that holes continue to play a role in the degradation physics at low voltages. However, our experiments eliminate anode hole injection as the mechanism for breakdown below about 2.7V. • Plasma nitridation of oxides significantly extends the reliability scaling limit of SiO2 based films. Bulk trap generation rates are minimized and the film reliability is optimized when the nitrogen profile is uniform. Plasma nitrided SiON films are now widely used throughout the industry in high volume manufacturing. • Reaction-diffusion theory applies for TDDB stress of ultra-thin NMOS SiON films. Measurable recovery effects are present, showing that quasi-equilibrium exists for NMOS under substrate injection conditions. This finding enables the determination of the mechanisms for trap generation and breakdown, showing that they are controlled by the release of two species of hydrogen (H+ and H0) from the anode in two separate anode reactions. H+ and H0 both create interface traps at the poly interface when they are released. After migrating into the dielectric, H+ subsequently creates SiON bulk traps while H0 subsequently creates interface traps at the pwell interface. The hydrogen species that controls breakdown is voltage dependent. The mechanism for breakdown transitions from hole induced H+ desorption to electron induced H0 desorption below the 2.7V threshold for vibrational excitation of Si-H bonds. • Bulk traps control breakdown in SiO2 dielectrics below 30Å. However, bulk traps are not always the defects that control breakdown in SiON films below 20Å. Below the 2.7V threshold energy for vibrational excitation of silicon-hydrogen bonds, the rate limiting step is the generation of interface traps. However, a minimum of two traps is required to cause breakdown in SiON films down to 10Å EOT. At least one trap must be an interface state and at least one must be a bulk state. • Our experimentally obtained trap generation power law exponent m being about 0.3, which is lower than the numbers reported by other researchers, is the only value that is consistent with the temperature and voltage dependence of trap generation and breakdown. This leads to the SiON bulk trap diameter being about 4Å, which is significantly lower than earlier estimates and results in the Weibull slope to remain greater than 1 down to the 12Å limit for physical oxide thickness
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