1,720,993 research outputs found
Leveraging domain knowledge for the efficient design-space exploration of advanced cyber-physical systems
Get PDFCyber-physical systems are becoming increasingly complex. In these advanced systems, the different engineering domains involved in the design process become more and more intertwined. In these situations, a traditional (sequential) design process becomes inefficient in finding good designs options. Instead, an integrated approach is needed where parameters in both the control and embedded domain can be chosen, evaluated and optimized to have a good solution in both domains. However, in such an approach, the combined design space becomes vast. As such, methods are needed to mitigate this problem. In this paper, we show how domain knowledge can be used to guide the design-space exploration process for an advanced control system and its deployment on embedded hardware. We use domain knowledge, captured in an ontology, to reason about the relationships between parameters in the different domains. This leads to a stepwise design space-exploration process where this domain knowledge is used to quickly reduce the design space to a subset of likely good candidates. In this process, we make use of cross-domain evaluation to find feasible design options with good system-level performance
Platform independent software analysis for near memory computing
Get PDFNear-memory Computing (NMC) promises improved performance for the applications that can exploit the features of emerging memory technologies such as 3D-stacked memory. However, it is not trivial to find such applications and specialized tools are needed to identify them. In this paper, we present PISA-NMC, which extends a state-of-the-art hardware agnostic profiling tool with metrics concerning memory and parallelism, which are relevant for NMC. The metrics include memory entropy, spatial locality, data-level, and basic-block-level parallelism. By profiling a set of representative applications and correlating the metrics with the application's performance on a simulated NMC system, we verify the importance of those metrics. Finally, we demonstrate which metrics are useful in identifying applications suitable for NMC architectures
Model-based processor-in-the-loop framework for composable multi-core platforms
No full text\u3cp\u3eFrom model-based design to implementation on an embedded platform requires target-specific code generation, compilation, and execution. Processor-in-the-loop (PIL) simulation is an intermediate step meant for detailed testing and debugging in the development process. This paper presents a PIL simulation framework targeting multi-core FPGA-based embedded platforms. The presented framework allows for a fully automated process of performing PIL simulations on an FPGA-based embedded platform - CompSOC - starting from a Simulink model. The framework includes two PIL configurations - one configuration executes only the controller code on the target platform while other configuration executes both the controller and the plant code on the target platform. It considers scheduling of multiple applications and interference-free execution on the target platform under the PIL configurations. Further, the framework allows for logging various measurements of parameters such as execution time, memory usage and so on in the PIL configurations which can be used for testing and debugging purposes.\u3c/p\u3
System Design of an Open-Source Cloud-Based Framework for Internet of Drones Application
No full textUnmanned Aerial Vehicles (UAV) are increasingly gaining interest in Internet of Drones (IoD) applications for automatizing the labor-intensive tasks. They are used in various areas such as infrastructure inspection. However, UAVs have limited energy resources and computational processing capabilities, which prevents them from running applications onboard and accessing the internet for gaining knowledge about their mission. In order to address these challenges imposed by limited resource on the drone, we propose a new cloud system infrastructure for building open-source IoD applications. We have designed a client-server architecture which hosts the drone as a client and the cloud as a scalable server. For validating the developed IoD application, an open-source drone simulator and flight controller are adopted to perform the tests. The overall architecture of a drone-cloud framework is presented along with a use case to show the applicability of the proposed framework.</p
Keyword Spotting using Time-Domain Features in a Temporal Convolutional Network
No full textWith the increasing demand on voice recognition services, more attention is paid to simpler algorithms that are capable to run locally on a hardware device. This paper demonstrates simpler speech features derived in the time-domain for Keyword Spotting (KWS). The features are considered as constrained lag autocorrelations computed on overlapped speech frames to form a 2D map. We refer to this as Multi-Frame Shifted Time Similarity (MFSTS). MFSTS performance is compared against the widely known Mel-Frequency Cepstral Coefficients (MFCC) that are computed in the frequency-domain. A Temporal Convolutional Network (TCN) is designed to classify keywords using both MFCC and MFSTS. This is done by employing an open source dataset from Google Brain, containing ~ 106000 files of one-second recorded words such as, 'Backward', 'Forward', 'Stop' etc. Initial findings show that MFSTS can be used for KWS tasks without visiting the frequency-domain. Our experimental results show that classification of the whole dataset (25 classes) based on MFCC and MFSTS are in a very good agreement. We compare the performance of the TCNbased classifier with other related work in the literature. The classification is performed using small memory footprint (~ 90 KB) and low compute power (~ 5 MOPs) per inference. The achieved classification accuracies are 93.4% using MFCC and 91.2% using MFSTS. Furthermore, a case study is provided for a single-keyword spotting task. The case study demonstrates how MFSTS can be used as a simple preprocessing scheme with small classifiers while achieving as high as 98% accuracy. The compute simplicity of MFSTS makes it attractive for low power KWS applications paving the way for resource-aware solutions.</p
Fault Tolerant FPGAs: Where to Spend the Effort?
No full textStatic Random-Access Memory-based (SRAM-based) Field-Programmable Gate Arrays (FPGAs) are widely used in reallife applications, such as autonomous driving, high tech systems, and in space, where high dependability is a mandatory requirement. Since FPGA designs are stored in the Configuration Memory (CM) in SRAM-based FPGAs, they are very sensitive to Single Event Upsets (SEUs). Thus, adapting FPGA designs to make them more Fault Tolerant (FT) is extremely important. FT techniques introduce additional penalties in system parameters, like area, power consumption and performance. In order to tradeoff between the overhead introduced by FT techniques and system robustness, an accurate estimation of CM vulnerability to SEUs is needed. Many intrinsic error tolerant applications can tolerate in-exact output values to some degree. This paper shows how to exploit this property in making much cheaper FT FPGA designs with less overhead. For instance, our method can remove 51% of the area overhead for less than 0.048% output degradation, when considering a 32-bit FT adder FPGA design by applying Triple Modular Redundancy. We verify our results on various FPGA designs using a ZedBoard.</p
Timing Prediction for Service-Based Applications Mapped on Linux-Based Multi-core Platforms
No full textWe develop a model-based approach to predict timing of service-based software applications on Linux-based multi-core platforms for alternative mappings (affinity and priority settings). Service-based applications consist of communicating sequential (Linux) processes. These processes execute functions (also called services), but can only execute them one at a time. Models are inferred automatically from execution traces to enable timing optimization of existing (legacy) systems. Our approach relies on a linear progress approximation of functions. We compute the expected share of each function based on the mapping (affinity and priority) parameters and the functions that are currently active. We validate our models by carrying out a controlled lab experiment consisting of a multi-process pipelined application mapped in different ways on a quadcore Intel i7 processor. A broad class of affinity and priority settings is fundamentally unpredictable due to Linux binding policies. We show that predictability can be achieved if the platform is partitioned in disjoint clusters of cores such that i) each process is bound to such a cluster, ii) processes with non real-time priorities are bound to singleton clusters, and iii) all processes bound to a non-singleton cluster have different real-time priorities. For mappings using singleton clusters with niceness priorities only, our model predicts execution latencies (for each pipeline iteration) with errors less than 5% relative to the measured execution times. For mappings using a non-singleton cluster (with different real-time priorities) relative errors of less than 2% are obtained. When real-time and niceness priorities are mixed, we predict with errors of 7%.</p
An Application of Hyper-Heuristics to Flexible Manufacturing Systems
No full textContains fulltext :
209224.pdf (Publisher’s version ) (Closed access)DSD 2019: Euromicro Conference on Digital System Design, 28 - 30 August 2019 Kallithea, Chalkidiki, Greec
Compositional Dataflow Modelling for Cyclo-Static Applications
No full textModular design is a common practice when designing complex applications for embedded systems. Another important practice in the embedded systems domain is the use of abstract models to realize predictable behaviour. Modular model-based design allows to construct a modular model of a complex system via model composition. The model of computation considered in this paper is scenario-aware dataflow, a dataflow model that allows for dynamic behaviour. We model applications with behaviour that changes according to a periodic pattern. Composing models with periodic patterns results in a model with a periodic pattern with a common hyper-period. We propose an efficient algorithmic method to compose cyclo-static scenario-aware dataflow models by generating composite patterns in a concise representation. We show that our approach can automatically generate concise models of several real-life image processing applications.</p
Inter-patient ECG classification using deep convolutional neural networks
No full textIn this paper we present fully automatic interpatient electrocardiogram (ECG) signal classification method using deep convolutional neural networks (CNN). ECG is simple and non-invasive way to measure the electric activity of the heart and it provides valuable information about the condition of the heart. It is widely utilized for detecting different abnormalities in heartbeat. Identifying and classification abnormalities is timeconsuming, because it often requires analyzing each heartbeat of the ECG recording. Therefore, automatic classification of the arrhythmias using machine-learning technologies can bring various benefits. In this paper, we are focusing on inter-patient arrhythmia classification, where separate patient data is used in training and test phase. This method is more realistic in clinical environment, where trained model needs to operate with patients, whose ECG data was not available during the training phase. Our proposed method gives 92% sensitivity, 97% positive predictivity and 23% false positive rate for normal heartbeats. For supraventricular ectopic beat, our approach gives 62% sensitivity, 56% positive predictivity and 2% false positive rate. For ventricular ectopic beat, our method gives 89% sensitivity, 51% positive predictivity and 6% false positive rate. These results from our fully automatic feature learning approach are on par with solutions that require manual feature engineering.</p
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