57 research outputs found
User-Level DMA without Operating System Kernel Modification
No full textDirect Memory Access (DMA) is frequently used to transfer data between the main memory of a host computer and the interconnection network, in order to free the host processor from the burden of the transfer. DMA operations are traditionally initiated by the operating system kernel, mainly to prevent one application from tampering with another applications' data. Recent architecture trends suggest that interconnection networks get faster, while operating systems get slower (compared to processor speeds). These trends imply that the initiation of a DMA operation becomes slower (due to operating system involvement), while the DMA data transfer itself becomes faster with time. Soon, the operating system overhead associated with starting a DMA will be larger than the data transfer itself, esp. for small data transfers. This paper proposes several algorithms that allow user-level applications to start DMA operating without the involvement of the operating system. Our algorithms allow user ap..
ATLAS I: A Single-chip ATM switch for NOWs
No full text. Although ATM (Asynchronous Transfer Mode), is a widely accepted standard for WANs (Wide Area Networks), it has not yet been widely embraced by the NOW community, because (i) most current ATM switches (and interfaces) have high latency, and and (ii) they drop cells when (even short-term) congestion happens. In this paper, we present ATLAS I, a single-chip ATM switch with 20 Gbits/sec aggregate I/O throughput, that was designed to address the above concerns. ATLAS I provides sub-microsecond cut-through latency, and (optional) backpressure (credit-based) flow control which never drops ATM cells. The architecture of ATLAS I has been fully specified and the design of the chip is well under progress. ATLAS I will be fabricated by SGS Thomson, Crolles, France, in 0.5 ¯m CMOS technology. 1 Introduction Popular contemporary computing environments are comprised of powerful workstations connected via a high-speed network, giving rise to systems called workstation clusters or Networks of Worksta..
Fluid structure interaction modelling on flapping wings
No full textFlapping wings display complex flows which can be used to generate large lift forces. Flexibility in wings is widely used by natural flyers to increase the aerodynamic performance. The influence of wing flexibility on the flow can be computed using numerical analysis with Fluid Structure Interaction (FSI). The influence of inertial, elastic and aerodynamic forces is quantified using a 2D wing. A sinusoidal flapping motion is imposed on the leading edge of the vertical wing. The inertial force on the wing dominates for high mass ratios and the wing deflection is rather independent of the flow. For a low mass ratio, the wing deformation scales with the increasing elasticity. The maximum lift and lowest drag were found for the wing with large flexibility and low mass so the passive deformation by aerodynamic forces creates a favourable shape for lift production. Flexible translating and revolving wings at an angle of attack of 45 degrees show that chordwise flexibility decreases both lift and drag, however the lift over drag ratio is increased. The flow around both wings forms a coherent structure with a Root Vortex (RV), Tip Vortex (TV), Leading Edge Vortex (LEV) and Trailing Edge Vortex (TEV). The LEV on the revolving wing is stable for approximately up to half the span because vorticity is transported outward in the vortex core. The flowfield and LEV breakdown are consistent with experimental data of the same wing. The translating wing builds up circulation but the LEV detaches quickly near the centre of the wing. Chordwise bending reduces the angle of attack which decreases the distance to the core of the shed LEVs.Aerodynamic
The remote enqueue operation on networks of workstations
No full textAbstract. Modern networks of workstations connected by Gigabit networks have the ability to run high-performance computing applications at a reasonable performance, but at a signi cantly lower cost. The performance of these applications is usually dominated by their e ciency of the underlying communication mechanisms. However, e cient communication requires that not only messages themselves are sent fast, but also noti cation about message arrival should be fast as well. For example, a message that has arrived at its destination is worthless until the recipient is alerted to the message arrival. In this paper we describe a new operation, the remote-enqueue atomic operation, which can be used in multiprocessors, and workstation clusters. This operation atomically inserts a data element in a queue that physically resides in a remote processor's memory. This operation can be used for fast noti cation of message arrival, and for fast passing of small messages. Compared to other software and hardware queueing alternatives, remote-enqueue provides high speed at a low implementation cost without compromising protection in a general-purpose computing environment.
Telegraphos: High-Performance Networking for Parallel Processing on Workstation Clusters
No full textNetworks of workstations and high-performance microcomputers have been rarely used for running highperformance applications like multimedia, simulations, scientific and engineering applications, because, although they have significant aggregate computing power, they lack the support for efficient message-passing and shared-memory communication. In this paper we present Telegraphos, a distributed system that provides efficient shared-memory support on top of a workstation cluster. We focus on the network interface of Telegraphos that provides a variety of shared-memory operations like remote reads, remote writes, remote atomic operations, all launched from user level without any intervention of the operating system. Telegraphos I, the first Telegraphos prototype has been implemented. Emphasis was put on rapid prototyping, so the technology used was conservative: FPGA's, SRAM's, and TTL buffers. Telegraphos II, is the single-chip version of the Telegraphos architecture; its switch was im..
On the investigation of utility functions on optimal sensor locations
No full textStructural Health Monitoring uses data collected from sensors placed on structures to determine their operating condition and whether maintenance is required. Often, optimal sensor placement strategies are used to find the optimal locations for the identification of their modal properties, structural parameters and/or abnormal behaviours under the influence of model and measurement uncertainty. An approach that has been frequently used to solve the problem of sensor placement is the Bayesian experimental design. This approach chooses the locations using the data measured by the sensors to reduce the prior uncertainty of the parameters that are being inferred. The Bayesian experimental design minimizes the uncertainty of the parameters to be inferred through the use of metrics called utility functions. Most of these metrics are based on functions of the posterior distribution. In this paper, the use of three utility functions (Bayesian D-posterior precision, Bayesian A-posterior precision, and Expected Information Gain) is investigated for the problem of sensor placement. The case study chosen consists of a beam with translational and rotational springs connected to the ground subject to an impulsive load. The goal of the analysis is to select the most informative position of a sensor in order to update the distribution of two uncertain physical parameters of the beam based on natural frequencies extracted using the Eigensystem Realization Algorithm. It is shown that for the case investigated, the three utility functions yield the same optimal sensor location.Mechanics and Physics of Structure
Modeling Energy-Performance Tradeoffs in ARM big. LITTLE Architectures
No full textHeterogeneous multicores provide alternative core types and potentially multiple voltage-frequency levels to execute workloads more efficiently. One fundamental obstacle for capitalizing their potential performance and energy gains is identifying the most appropriate configuration (core type and voltage-frequency pair) for executing the computations at hand. In this paper, we analyze an ARM big. LITTLE architecture and show that the most efficient configuration is not always the expected one. We study the performance and energy tradeoffs of the big and the LITTLE ARM cores at different voltage and frequency levels. To do so we use various workloads and observe the overheads and benefits from using one configuration over another. Subsequently, we investigate how the workload characteristics and their execution on a particular core type affect energy consumption. We develop a lightweight energy model, suitable for runtime use, to accurately capture the above tradeoffs. Our model uses as input parameters only the instructions per cycle (IPC) and instruction mix. We evaluate the accuracy of the model across the two core types, different frequencies and various benchmarks. The model is able to predict the changes in the energy consumption of a program when moving from one configuration to another with an average error of 4.7%. Moreover, it is able to sort correctly 96% of the configurations across all benchmarks based on their energy consumption. Finally, our energy model can predict correctly for 22 out of 26 benchmarks the configuration that minimizes the energy-delay product (EDP); in the remaining four benchmarks the increase in EDP is less than 2.46%
Variable packet size buffered crossbar (cicq) switches
No full textAbstract — One of the most widely used architectures for packet switches is the crossbar. A special version of it is the buffered crossbar, where small buffers are associated with the crosspoints; this simplifies scheduling and improves its efficiency and QoS capabilities to the point where the switch needs no internal speedup. Furthermore, by supporting variable length packets throughout a buffered crossbar: (a) there is no need for segmentation and reassembly (SAR) circuits; (b) no speedup is necessary to support SAR; and (c) synchronization between the input and output clock domains is simplified. In turn, the lack of SAR and speedup mean that no output queues are needed, either. In this paper we present an architecture, a chip layout and cost analysis, and a performance evaluation of such a 300 Gbps buffered crossbar operating on variable-size packets. The proposed organization is simple yet powerful, can be implemented using modern technology, and, as the performance results demonstrate, it clearly outperforms unbuffered crossbars.
- …
