1,721,071 research outputs found
Total cost of ownership perspective of Cloud vs Edge deployments of IoT applications
No full textThe number of intelligent Internet-connected devices is growing rapidly and will soon be in the order of tens of billions, forming the Internet of Things (IoT). Each of these devices is pushing data to the Internet that are soon expected to reach tens of exabytes. It is expected that such data growth will put an unprecedented pressure on the current Internet infrastructure and the centralized (Cloud) data centers (DCs). In order to successfully deal with this imminent data flood, it is imperative to enhance the processing capabilities of the current servers. Redesigning data communication and processing across the Internet is equally important. Additionally, a new paradigm has emerged which makes Cloud services available at the Edge. One key ramification of these developments is an increase in the cost of both Cloud and Edge DCs. The main goal of this chapter is to improve the Total cost of Ownership (TCO) of Edge and Cloud deployments by discovering the capability of the underlying hardware components to function beyond nominal operating points. By taking the advantage of the extended operating margins, inherent to processors and memories, it is possible to improve the power efficiency of servers running in the Cloud or Edge. The successful exploitation of these margins will lead to significant cost savings. Thus, in this chapter we present an End-to-End TCO tool to evaluate two IoT applications. In order to come up with an End-to-End TCO evaluation, we have firstly determined the requirements and parameters of each of the two applications. Furthermore, the metrics of success related to each application have been determined as well. For instance, to evaluate Polaris application, we use TCO under various constraints, and for Social CRM we use TCO over client’s degree of satisfaction in square metric.<br/
Software engineering for edge computing
No full textEdge computing has been recently introduced by both industry and academia to quench the need for a computing paradigm close to mobile devices. Edge computing bridges the gap between the cloud and mobile devices by enabling computing, storage, networking, and data management in edge nodes within the close vicinity of end users’ devices. While there are various surveys about Edge computing in the literature, what is currently missing is the description of the software-engineering aspects of the applications that are built/deployed via the edge. The contribution of the current chapter is twofold. We first highlight the software-engineering aspects of the current edge-computing approaches. In particular, we specify the core concepts of the general-purpose software-engineering process, the multi-tier architecture of edge infrastructure, and how software applications are deployed to such an infrastructure. Secondly, we abstract a software-engineering process suitable for edge computing and we outline the research challenges in this process.<br/
Going Beyond Counting First Authors in Author Co-citation Analysis
Get PDFThe present study examines one of the fundamental aspects of author co-citation analysis (ACA) - the way co-citation
counts are defined. Co-citation counting provides the data on which all subsequent statistical analyses and mappings
are based, and we compare ACA results based on two different types of co-citation counting - the traditional type that
only counts the first one among a cited work's authors on the one hand and a non-traditional type that takes into
account the first 5 authors of a cited work on the other hand. Results indicate that the picture produced through this non-traditional author co-citation counting contains more coherent author groups and is therefore considerably clearer. However, this picture represents fewer specialties in the research field being studied than that produced through the traditional first-author co-citation counting when the same number of top-ranked authors is selected and analyzed. Reasons for these effects are discussed
Variations on the Author
Get PDF“Variations on the Author” discusses two of Eduardo Coutinho’s recent films (Um Dia na Vida, from 2010, and Últimas Conversas, posthumously released in 2015) and their contribution to the general question of documentary authorship. The director’s filmography is characterized by a consistent yet self-effacing form of authorial self-inscription: Coutinho often features as an interviewer that rather than express opinions propels discourses; an interviewer that is good at listening. This mode of self-inscription characterizes him as an author who is not expressive but who is nonetheless markedly present on the screen. In Um Dia na Vida, however, Coutinho is completely absent form the image, while Últimas Conversas, on the contrary, includes a confessional prologue that moves the director from the margins to the center of his films. This article examines the ways in which these works stand out in the filmography of a director who offers new insights into the notion of cinematic authorship
Appropriate Similarity Measures for Author Cocitation Analysis
Get PDFWe provide a number of new insights into the methodological discussion about author cocitation analysis. We first argue that the use of the Pearson correlation for measuring the similarity between authors’ cocitation profiles is not very satisfactory. We then discuss what kind of similarity measures may be used as an alternative to the Pearson correlation. We consider three similarity measures in particular. One is the well-known cosine. The other two similarity measures have not been used before in the bibliometric literature. Finally, we show by means of an example that our findings have a high practical relevance.information science;Pearson correlation;cosine;similarity measure;author cocitation analysis
Cross-layer design methodologies for energy efficient and variation tolerant circuits and systems
No full textThe demand for richer services, multifunctional portable devices and high data rates can be only envisioned due to the improvements in semiconductor technology. Unfortunately, sub-90 nm process nodes uncover the nanometer Pandora-box exposing the barriers of technology scaling - increased power dissipation and parametric variations. The contradictory design requirements of these issues makes the development of low power and robust systems one of the most challenging design problem today. To that effect, we present cross-layer methodologies that address low power and variation-tolerance with low-overhead, at the system level where it is possible to effectively trade-off circuit level metrics such as power and delay with system level metrics such as quality-of-results and tolerance-to-variations. The proposed techniques exploit algorithmic properties to modify the computational complexity of digital signal processing systems in order to tackle delay failures, the common symptoms of parametric variations and voltage over-scaling, which is very effective in power reduction. The principal idea is to protect the significant computations of an algorithm that contribute significantly to the output quality by combining circuit/architecture techniques ensuring that any delay failure will affect only the less contributive computations, thereby leading to minor/acceptable quality degradation. The proposed significance driven design technique is applied to various types of designs that include logic and memory architectures and digital-signal-processing systems. Specifically, the technique is adopted to the design of ubiquitous logic blocks of DSP systems, FIR filters, color interpolation and discrete cosine transform architectures. Furthermore, a novel low power and robust embedded memory for multimedia applications is developed by combining the significance driven approach with circuit and architecture level memory design techniques. Finally, HERQULES, a unique and elegant mathematical solution to the exploration and identification of energy efficient techniques at the various levels of hardware stack that takes into consideration system level interactions between the blocks of a system is presented
Circuit-architecture co-design for low power and system lifetime enhancement through voltage over-scaling
No full textTemporal performance degradation due to Negative Bias Temperature Instability (NBTI) and corresponding lifetime enhancement has emerged as a critical challenge in design of integrated circuits (ICs) in the nanometer technology nodes. The existing circuit level NBTI estimation approaches have neglected the inter-dependency of parameters such as voltage and temperature and their impact on the circuit lifetime. In this thesis we present a model that self-consistently estimates the NBTI degradation in circuits by considering these parameters simultaneously. Using the proposed model, we observe that a circuit with lower voltage can provide better lifetime performance than with higher voltage. This interesting observation can be attributed to the reduction of electric field in the transistor along with the circuit power/temperature reduction that leads to lesser NBTI degradation. Based on this observation we have developed on-line detection and mitigation schemes that allow voltage over-scaling to enhance the system lifetime. Specifically, voltage over-scaling is achieved by utilizing circuit/architecture design techniques based on “elastic clocking” and “unequal error protection of computations”. By trading off minor system throughput penalty in general purpose processors or minor output quality degradation in application specific processors for voltage over-scaling, we can achieve system lifetime enhancement and lower power consumption
Retention Time Characterization of Commercial DRAM Modules Using an FPGA-based Test Platform
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