1,720,979 research outputs found
A Reconfigurable SOM Hardware Accelerator
Full text linkPorrmann M, Franzmeier M, Kalte H, Witkowski U, Rückert U. A Reconfigurable SOM Hardware Accelerator.A dynamically reconfigurable hardware accelerator for self-organizing
feature maps is presented. The system is based on the universal rapid prototyping system RAPTOR2000 that has been developed by the authors. The modular prototyping system is based on XILINX FPGAs and is capable of emulating hardware implementations with a complexity of more than 24 million system
gates. RAPTOR2000 is linked to its host – a standard personal computer or
workstation – via the PCI bus. For the simulation of self-organizing maps a module has been designed for the RAPTOR2000 system, that embodies an FPGA of the Xilinx Virtex series and optionally up to 128 MBytes of SDRAM. A speedup of about 50 is achieved with five FPGA modules on the RAPTOR2000 system compared to a software implementation on a state of the art personal computer for typical applications of self-organizing maps
Implementation of artificial neural networks on a reconfigurable hardware accelerator
No full textPorrmann M, Witkowski U, Kalte H, Rückert U. Implementation of artificial neural networks on a reconfigurable hardware accelerator. In: Parallel, Distributed and Network-based Processing, 2002. Proceedings. 10th Euromicro Workshop on. IEEE Comput. Soc; 2002: 243-250.The hardware implementation of three different artificial
neural networks is presented. The basis for the implementation
is the reconfigurable hardware accelerator
RAPTOR2000, which is based on FPGAs. The investigated
neural network architectures are neural associative
memories, self-organizing feature maps and basis function
networks. Some of the key implementational issues are
considered. Especially resource-efficiency and performance
of the presented realizations are discussed
Implementation of a RISC Processor Core for SoC Designs – FPGA Prototype vs. ASIC Implementation
Full text linkLangen D, Niemann J-C, Porrmann M, Kalte H, Rückert U. Implementation of a RISC Processor Core for SoC Designs – FPGA Prototype vs. ASIC Implementation. In: Proceedings of the IEEE-Workshop: Heterogeneous reconfigurable Systems on Chip (SoC). Hamburg, Germany; 2002.In this paper, an implementation of a RISC processor core for SoC designs is presented. We analyze
the differences between a prototypical FPGA implementation and standard cell realizations
in an 0.6μm and an 0.13μm technology, respectively. The core was developed by using
the hardware description language VHDL, which offers the opportunity of adding special, optimized
hardware blocks for various operations. The effects on area and power consumption as
well as computational power are analyzed. A detailed overview of the implementation of additional
hardware multipliers and their effects on the above mentioned topics concludes this paper
Going Beyond Counting First Authors in Author Co-citation Analysis
Full text linkThe present study examines one of the fundamental aspects of author co-citation analysis (ACA) - the way co-citation
counts are defined. Co-citation counting provides the data on which all subsequent statistical analyses and mappings
are based, and we compare ACA results based on two different types of co-citation counting - the traditional type that
only counts the first one among a cited work's authors on the one hand and a non-traditional type that takes into
account the first 5 authors of a cited work on the other hand. Results indicate that the picture produced through this non-traditional author co-citation counting contains more coherent author groups and is therefore considerably clearer. However, this picture represents fewer specialties in the research field being studied than that produced through the traditional first-author co-citation counting when the same number of top-ranked authors is selected and analyzed. Reasons for these effects are discussed
Variations on the Author
Full text link“Variations on the Author” discusses two of Eduardo Coutinho’s recent films (Um Dia na Vida, from 2010, and Últimas Conversas, posthumously released in 2015) and their contribution to the general question of documentary authorship. The director’s filmography is characterized by a consistent yet self-effacing form of authorial self-inscription: Coutinho often features as an interviewer that rather than express opinions propels discourses; an interviewer that is good at listening. This mode of self-inscription characterizes him as an author who is not expressive but who is nonetheless markedly present on the screen. In Um Dia na Vida, however, Coutinho is completely absent form the image, while Últimas Conversas, on the contrary, includes a confessional prologue that moves the director from the margins to the center of his films. This article examines the ways in which these works stand out in the filmography of a director who offers new insights into the notion of cinematic authorship
Appropriate Similarity Measures for Author Cocitation Analysis
Full text linkWe provide a number of new insights into the methodological discussion about author cocitation analysis. We first argue that the use of the Pearson correlation for measuring the similarity between authors’ cocitation profiles is not very satisfactory. We then discuss what kind of similarity measures may be used as an alternative to the Pearson correlation. We consider three similarity measures in particular. One is the well-known cosine. The other two similarity measures have not been used before in the bibliometric literature. Finally, we show by means of an example that our findings have a high practical relevance.information science;Pearson correlation;cosine;similarity measure;author cocitation analysis
Dispelling the Myths Behind First-author Citation Counts
Full text linkWe conducted a full-scale evaluative citation analysis study of scholars in the XML research field to explore just how different from each other author rankings resulting from different citation counting methods actually are, and to demonstrate the capability of emerging data and tools on the Web in supporting more realistic citation counting methods. Our results contest some common arguments for the continued
use of first-author citation counts in the evaluation of scholars, such as high correlations between author rankings by first-author citation counts and other citation
counting methods, and high costs of using more realistic citation counting methods that are not well-supported by the ISI databases. It is argued that increasingly available digital full text research papers make it possible for citation analysis studies to go beyond what the ISI databases have directly supported and to employ more
sophisticated methods
System-on-programmable-chip approach enabling online fine-grained 1D-placement
No full textKalte H, Porrmann M, Rückert U. System-on-programmable-chip approach enabling online fine-grained 1D-placement. In: Parallel and Distributed Processing Symposium, 2004. Proceedings. 18th International. IEEE; 2004: 141.The increasing logic density of current FPGAs (Field
Programmable Gate Arrays) enables the integration of
whole systems on one programmable chip. Some of these
FPGAs provide the additional feature of partial dynamic
reconfiguration, which permits to change parts of the
device while other parts keep working. Combining the
features of system level density and partial dynamic reconfiguration
enables the integration of dynamic systems
that can be adopted to changing demands during runtime.
A lot of theoretical work in this challenging research area
has been done on efficiently placing and scheduling modules
on the FPGA area. However, there is a lack of applied
approaches that can be realized by existing tools
and FPGAs. In this paper we present a new, realizable
approach for the dynamic system integration on Xilinx
Virtex FPGAs. In contrast to the existing approaches that
consider fixed slots for the module placement, our approach
enables the fine-grained placement of modules
with variable width along a horizontal communication
infrastructure
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