125,012 research outputs found
Going Beyond Counting First Authors in Author Co-citation Analysis
Get PDFThe present study examines one of the fundamental aspects of author co-citation analysis (ACA) - the way co-citation
counts are defined. Co-citation counting provides the data on which all subsequent statistical analyses and mappings
are based, and we compare ACA results based on two different types of co-citation counting - the traditional type that
only counts the first one among a cited work's authors on the one hand and a non-traditional type that takes into
account the first 5 authors of a cited work on the other hand. Results indicate that the picture produced through this non-traditional author co-citation counting contains more coherent author groups and is therefore considerably clearer. However, this picture represents fewer specialties in the research field being studied than that produced through the traditional first-author co-citation counting when the same number of top-ranked authors is selected and analyzed. Reasons for these effects are discussed
Dispelling the Myths Behind First-author Citation Counts
Get PDFWe conducted a full-scale evaluative citation analysis study of scholars in the XML research field to explore just how different from each other author rankings resulting from different citation counting methods actually are, and to demonstrate the capability of emerging data and tools on the Web in supporting more realistic citation counting methods. Our results contest some common arguments for the continued
use of first-author citation counts in the evaluation of scholars, such as high correlations between author rankings by first-author citation counts and other citation
counting methods, and high costs of using more realistic citation counting methods that are not well-supported by the ISI databases. It is argued that increasingly available digital full text research papers make it possible for citation analysis studies to go beyond what the ISI databases have directly supported and to employ more
sophisticated methods
The Mysterious Bipolar Bias Temperature Stress from the Perspective of Gate-Sided Hydrogen Release
No full textInvestigating the correlation between interface and dielectric trap densities in aged p-MOSFETs using current-voltage, charge pumping, and 1/f noise characterization techniques
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Impact of Heavy-Ion Strikes on Minimum-Size MOSFETs With Ultra-Thin Gate Oxide
No full textIn this work we have investigated the effects of irradiation and electrical stress of nanocrystal memory cell arrays. Heavy ion irradiation has no or negligible immediate effects on the nanocrystal MOSFET characteristics, and on the programming window of the cells. By electrically stressing irradiated device, we see accelerated oxide breakdown similar to that previously observed on conventional thin gate oxide MOS capacitors, but no appreciable change of the degradation kinetics in terms of programming window closure and shift. The accelerated breakdown is ascribed to the degradation of the oxide-nitride-oxide (ONO) layer used as control oxide after exposure to ionising irradiation
Defect spectroscopy from electrical measurements: A simulation based technique
No full textWe present in this paper a novel defect spectroscopy technique for extracting defect and material properties of gate oxides and dielectrics used for memory devices (e.g. DRAM, RRAM). The method is based on the correlate simulation of electrical characteristics (IV, CV, GV, BTI), to allow the determination of the energy distribution and depth profile of atomic defects within the material bandgap. This novel defect spectroscopy technique is applied to MOSFET gate stacks with Si and InGaAs, and to DRAM capacitors
The Mysterious Bipolar Bias Temperature Stress from the Perspective of Gate-Sided Hydrogen Release
No full textUnderstanding the potential and the limits of Germanium pMOSFETs for VLSI circuits from experimental measurements
No full textIn this paper, potential and limits of Germanium pMOSFETs for VLSI applications are investigated from a circuit perspective for the first time in the literature. Since short-channel Germanium devices have been developed only recently, no circuit design tools are currently available, hence most of the results available in the literature address process and device-level issues (currently, down to the 65 nm node). However, the suitability of Germanium MOSFETs for VLSI circuits should be assessed at circuit level. To fill this gap, we introduce an innovative methodology that extracts the main circuit parameters of interest (e. g., speed, dynamic power, leakage) from measurements on experimental devices. Appropriate figures of merit are adopted to highlight the potential of Germanium MOSFETs under realistic VLSI designs that fully exploit system-level schemes to minimize leakage (e. g., body biasing, stack forcing, power gating). Measurements and evaluations are performed on 125 nm Germanium pMOSFETs with a high-kappa/metal gate stack having an equivalent oxide thickness of 1.3 nm. Comparison with Si pMOSFET prototypes implemented with similar gate stack is also carried out to comparatively understand the potential and the weaknesses of Germanium transistors. The main experimental results are justified through theoretical analysis as a function of the relevant circuit and device parameters. Some system-level aspects are also investigated, such as the energy efficiency and the wakeup time of body-biasing schemes in Ge circuits and the impact of voltage scaling
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