1,720,961 research outputs found
Improving prediction performances by integrating second derivative in microgrids energy load forecasting
No full textAccurate forecasting in time series data is crucial, especially in the energy sector, where prediction precision significantly influences decision-making and operational efficiency. This study investigates the efficacy of integrating second derivative data into forecasting models for energy consumption. We employ four distinct energy consumption time series datasets, each exhibiting varied characteristics and trends. The core of our methodology is the innovative incorporation of second derivative data to improve the accuracy of energy forecasting. This approach is applied to two widely recognized forecasting algorithms: Long Short-Term Memory (LSTM) and Extreme Gradient Boosting (XGBoost). Our research introduces the second derivative of energy data as an additional input for these algorithms. This supplementary feature is used to provide deeper insight into the acceleration and deceleration trends in energy consumption, aspects often overlooked in standard models. We compare the performance of these enhanced models against their traditional counterparts, which do not utilize second derivative data. The results demonstrate a significant improvement in forecasting accuracy, particularly in peak regions, for both LSTM and XGBoost models with the inclusion of second derivative data. This research holds broad practical applications, notably in energy management systems and smart grid technologies, where it can contribute to more efficient energy distribution decisions
Single event transient reliability analysis on a fault-tolerant RISC-V microprocessor design
No full textThe miniaturization of electronic devices and the improved operating speeds increase the likelihood of single event faults. Differently from Single Event Upset (SEU) faults, Single Event Transient (SET) faults generally affect combinational logic, making all voting systems vulnerable to errors. The proposed work uses an ad-hoc fault-simulation campaign employing signal glitching to identify SET vulnerabilities inside a RISC-V core already equipped with resilience logic against Single Event Upset (SEU) faults. The faults target the majority voting logic structures, highlighting how they can be susceptible to faults depending on the width of the injected pulses, and showing how the use of Buffered Triple Modular Redundancy (BTMR) allows decreasing the total failure probability due to erroneous majority voters. © The Author(s), under exclusive license to Springer Nature Switzerland AG 2024
Implementation of dynamic acceleration unit exchange on a RISC-V soft-processor
No full textUsing Artificial Intelligence (AI) techniques has become the best solution in many applications. By the end of Moore's Law, implementing a platform capable of such massive processing for edge-IoT applications has become a significant challenge. However, using static hardware accelerators can be an excellent solution; even so, they typically require a great deal of silicon area and are not optimized for all operation modes. Reconfigurable computing lets parts of the hardware change proportionally to the task during operation, allowing for optimized operation and the use of many hardware accelerators without requiring a large area. In this study, we present a dynamic acceleration unit exchange on a RISC-V soft-processor based on the open-source Klessydra-T13 RISC-V core. We show how reconfiguration can be used to make the hardware accelerator more flexible and improve its performance. As a case study, we show how reconfiguration techniques can be used to speed up AI architectures by reconfiguration of vector accelerator units
Contextual bandits algorithms for reconfigurable hardware accelerators
No full textReconfigurable processing cores for IoT and edge computing applications are emerging topics to calibrate costs, energy consumption and area occupation with performance and reliability on Commercial Off the Shelf (COTS) devices. This work analyzes how to take advantage of Machine Learning to potentially automate the reconfiguration process of a hardware accelerator inside the Klessydra Vector Coprocessor Unit (VCU), choosing the best configuration according to the workload. The problem is modeled with a contextual bandits approach using the Linear UCB algorithms and validated with offline Python simulations
A universal hardware emulator for verification IPs on FPGA: a novel and low-cost approach
No full textEfficient and cost-effective functional verification strategies are more and more essential in digital integrated system design. This paper presents a low-cost approach to meet this challenge, introducing a universal hardware emulator designed for verifying various Intellectual Property (IP) cores on FPGA. We demonstrate the practicality and performance of this emulator through a use-case of verifying an advanced Integer Arithmetic Logic Unit (ALU) for the RISC-V ISA vector extension.
The process of integration and the results obtained from the verification are presented and discussed. Preliminary findings indicate that the emulator can perform more than 1.1 million tests per second. This research contributes to the advancement of hardware verification techniques, providing researchers, universities, and small businesses with an accessible and effective solution
Going Beyond Counting First Authors in Author Co-citation Analysis
Get PDFThe present study examines one of the fundamental aspects of author co-citation analysis (ACA) - the way co-citation
counts are defined. Co-citation counting provides the data on which all subsequent statistical analyses and mappings
are based, and we compare ACA results based on two different types of co-citation counting - the traditional type that
only counts the first one among a cited work's authors on the one hand and a non-traditional type that takes into
account the first 5 authors of a cited work on the other hand. Results indicate that the picture produced through this non-traditional author co-citation counting contains more coherent author groups and is therefore considerably clearer. However, this picture represents fewer specialties in the research field being studied than that produced through the traditional first-author co-citation counting when the same number of top-ranked authors is selected and analyzed. Reasons for these effects are discussed
Variations on the Author
Get PDF“Variations on the Author” discusses two of Eduardo Coutinho’s recent films (Um Dia na Vida, from 2010, and Últimas Conversas, posthumously released in 2015) and their contribution to the general question of documentary authorship. The director’s filmography is characterized by a consistent yet self-effacing form of authorial self-inscription: Coutinho often features as an interviewer that rather than express opinions propels discourses; an interviewer that is good at listening. This mode of self-inscription characterizes him as an author who is not expressive but who is nonetheless markedly present on the screen. In Um Dia na Vida, however, Coutinho is completely absent form the image, while Últimas Conversas, on the contrary, includes a confessional prologue that moves the director from the margins to the center of his films. This article examines the ways in which these works stand out in the filmography of a director who offers new insights into the notion of cinematic authorship
Appropriate Similarity Measures for Author Cocitation Analysis
Get PDFWe provide a number of new insights into the methodological discussion about author cocitation analysis. We first argue that the use of the Pearson correlation for measuring the similarity between authors’ cocitation profiles is not very satisfactory. We then discuss what kind of similarity measures may be used as an alternative to the Pearson correlation. We consider three similarity measures in particular. One is the well-known cosine. The other two similarity measures have not been used before in the bibliometric literature. Finally, we show by means of an example that our findings have a high practical relevance.information science;Pearson correlation;cosine;similarity measure;author cocitation analysis
Automatic hardware accelerators reconfiguration through linearUCB algorithms on a RISC-V processor
No full textReconfigurable processors are hardware architectures that allow for the dynamic configuration of processing resources to optimize performance and power consumption, using partial reconfiguration to modify a portion of the design or update it without affecting the entire system. In this work, we present an automatic reconfiguration technique that leverages machine learning (ML) algorithms to automatically select the optimal configuration of a general-purpose hardware accelerator according to the workload and reconFigure the architecture at run-time. The problem is formulated as a Contextual Bandit (CB) case using the Linear Upper Confidence Bound (LinearUCB) algorithms and verified using the RISC-V Klessydra family cores as a case of study
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