75 research outputs found
Elektronism : en flerårig resa genom tolv månader
No full textTemat i boken Elektronism ligger i tiden. Staffan Holmbring och J Jacob Wikner gör en tidsresa genom året. Funderingar kopplas ihop med månadernas karaktär. Naturvetenskapliga och filosofiska tankar uppstår och läsaren får följa dem under tidsresans gång. Elektronism tar vid där vår frågvishet slutar. Holmbring och Wikner ställer frågor på ett enkelt vis. Varför är vatten blött? Varför blir det aldrig blötare av att vattna på vatten?Elektronism är en fristående fortsättning där den förra boken Elektrosofi slutade. Resan har nu fortsatt från geografiska stopp till stopp i vår kalender. Staffan Holmbring är teknisk doktor i tillämpad fysik från Linköpings universitet. Kompetensen han fick därifrån har han bland annat använt i de företag som han har drivit från 80-talet med verksamheter inom tillämpad fysik och integrerad elektronik. Mycket intresserar honom utanför det naturvetenskapliga skrået, främst litteratur, filosofi och bildkonst. J Jacob Wikner är uppväxt i Borgholm, Öland. Dagarna fylls ofta med föreläsningar, kretskonstruktion och forskningsprojekt som spänner från den afrikanska landsbygden via kroppens elektriska signaler till röntgendetektorer. Intressena för en teknisk doktor, docent och biträdande professor kan vara många.</p
Power consumption of analog circuits : a tutorial
No full textA systematic approach to the power consumption of analog circuits is presented. The power consumption is related to basic circuit requirements, as dynamic range, bandwidth, noise figure and sampling speed and is considering basic device and device scaling behavior. Several kinds of circuits are treated, as samplers, amplifiers, filters and oscillators. The objective is to derive lower bounds to power consumption in analog circuits, to be used as design targets when designing power-constrained analog systems.The original publication is available at www.springerlink.com: Christer Svensson and Jacob Wikner, Power consumption of analog circuits: a tutorial, 2010, ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING, (65), 2, 171-184. http://dx.doi.org/10.1007/s10470-010-9491-7 Copyright: Springer Science Business Media http://www.springerlink.com/</p
Frequency Compensation of High-Speed, Low-Voltage CMOS Multistage Amplifiers
No full textAamir SA, Harikumar P, Wikner JJ. Frequency Compensation of High-Speed, Low-Voltage CMOS Multistage Amplifiers. In: 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013). Piscataway, NJ: IEEE; 2013: 381-384.This paper presents the frequency compensation of high-speed, low-voltage multistage amplifiers. Two frequency compensation techniques, the Nested Miller Compensation with Nulling Resistors (NMCNR) and Reversed Nested Indirect Compensation (RNIC), are discussed and employed on two multistage amplifier architectures. A four-stage pseudo-differential amplifier with CMFF and CMFB is designed in a 1.2 V, 65-nm CMOS process. With NMCNR, it achieves a phase margin (PM) of 59° with a DC gain of 75 dB and unity-gain frequency (fug) of 712 MHz. With RNIC, the same four-stage amplifier achieves a phase margin of 84°, DC gain of 76 dB and fug of 2 GHz. Further, a three-stage single-ended amplifier is designed in a 1.1-V, 40-nm CMOS process. The three-stage OTA with RNIC achieves PM of 81°, DC gain of 80 dB and fug of 770 MHz. The same OTA achieves PM of 59° with NMCNR, while maintaining a DC gain of 75 dB and fug of 262 MHz. Pole-splitting, to achieve increased stability, is illustrated for both compensation schemes. Simulations illustrate that the RNIC scheme achieves much higher PM and fug for lower values of compensation capacitance compared to NMCNR, despite the growing number of low voltage amplifier stages
Kytkettyihin kapasitansseihin perustuvien vahvistimien asettumisajan nopeuttaminen analogia-digitaalimuuntimissa
No full textAbstractThe goal of this dissertation was to study and model the settling transient response of switched-capacitor (SC) circuit, which is the most important building block of Analog-to-Digital converters (ADCs), and to improve the settling performance of the SC circuit implemented in ADC in CMOS technology.In the design of the SC circuit, there are common obstacles in obtaining a precise and fast settling with low power consumption. The main contribution of this thesis is to speed up different SC circuits without adding extra power consumption or to achieve the required settling precision with low power consumption.Two solutions to reduce the power consumption of SC integrators in sigma-delta (SD) ADCs were designed and verified by simulations. These implementations are based on the passive charge redistribution technique by injecting a precalculated open-loop charge in the output of the first integrator. The injected charge was implemented either by a continuous function of the input and feedback voltages or by quantizing to three levels. In both cases, the idea is to minimize the initial transient voltage in the input of the first OTA and hence bypass the slewing of the OTA.Another approach was proposed for the traditional SC residue circuit of the pipeline ADC, where a load capacitor is connected to the output during the evaluation phase. Here, a pre-charge of the load capacitance can be used. One proposed implementation is called the continuously controlled pre-charged technique. It pre-charges the load capacitor to the proper voltage during the previous phase, connects the pre-charged load capacitor to the output of the OTA during the evaluation phase, and hence pulls the charge sharing so that the initial input step of the OTA is instantaneously minimized. The other implementation called the minimal pre-charged method implemented for the SC residue circuit of the pipeline ADC is to simply pre-charge the load capacitor with the fixed existing voltage, minimized the spread of the initial input voltage. This proposed technique did not require any additional active components.Original papersOriginal papers are not included in the electronic version of the dissertation.Sun, J., Rahkonen, T., & Neitola, M. (2012). Behavioral modeling of nonlinear settling for multiple cascaded SC stages. Proceeding of the IEEE NORCHIP Conference (NORCHIP’ 2012), Copenhagen, Denmark, 12-13 November 2012 (pp. 1-6). https://doi.org/10.1109/NORCHP.2012.6403136Sun, J., & Rahkonen, T. (2016). Solving the initial voltage of settling in switched-capacitor circuits. Proceeding of the IEEE International Instrumentation and Measurement Technology Conference (I2MTC’2016), Taipei, Taiwan, 23-26 May 2016 (pp. 1-4). https://doi.org/10.1109/I2MTC.2016.7520501Sun, J., & Rahkonen, T. (2018). Two capacitive-pulling techniques to aid the settling of SC residue amplifier. Proceeding of the IEEE International Instrumentation and Measurement Technology Conference (I2MTC’2018), Houston, Texas, USA, 14-17 May 2018 (pp. 1-4). https://doi.org/10.1109/I2MTC.2018.8409537Self-archived versionSun, J., & Rahkonen, T. (2019). Speed up technique by pre-charging load capacitor in SC residue circuit. IEEE Transactions on Circuits and Systems, Express Briefs, 66(4), 522-526. https://doi.org/10.1109/TCSII.2018.2864596Self-archived versionSun, J., & Rahkonen, T. (2019). Continuously controlled and discrete-level charge pumping techniques implemented in SC integrators. Analog Integrated Circuits and Signal Processing, 100(3), 653-661. https://doi.org/10.1007/s10470-019-01460-8Self-archived versionTiivistelmäKytkettyihin kapasitansseihin (SC-tekniikka) perustuvat vahvistimet ovat CMOS-tekniikkaan perustuvien analogia-digitaalimuuntimien (AD-muunnin) tärkeimpiä osia. Tämän väitöstyön tavoitteena oli tutkia ja mallittaa SC-tekniikkaan perustuvien vahvistinpiirien asettumisaikaa, ja etsiä piiriteknisiä keinoja asettumisajan nopeuttamiseksi.SC-piirien suunnittelun suurimpia ongelmia on saavuttaa tarkka ja nopea asettuminen mahdollisimman pienellä tehonkulutuksella. Tämän työn päätuloksina on joukko keinoja, joilla voidaan nopeuttaa SC-kytkettyjen vahvistimien asettumista ilman että niiden tehonkulutusta lisätään, tai saavuttaa aiempi suorituskyky pienemmällä tehonkulutuksella. Menetelmät perustuvat siihen, että SC-piirin passiivista varausjakautumista ohjataan niin, että vahvistimen tulosolmussa oleva transientti minimoituu, jolloin vahvistin ei ajaudu virtarajoitteiselle toiminta-alueelle, vaan sen asettuminen nopeutuu merkittävästi.Sigma-delta-tyyppiset AD-muuntimet koostuvat SC-integraattoreista, ja näiden asettumisen nopeuttamiseen kehitettiin ja varmennettiin simuloiden kaksi tapaa. Varauksen jakautumista autettiin syöttämällä erillisellä varauspumpulla transkonduktanssivahvistimen lähtösolmuun tietty, integraattorin tilasta ja tuloista riippuva varaus. Tällöin vahvistimen tulossa näkyvä alkutransientti pienenee, ja vahvistin ei ajaudu virtarajoitteiselle toiminta-alueelleen, jolloin sen asettumisvirhe pienenee merkittävästi. Varausinjektio toteutettiin kahdella eri tavalla: laskemalla tarvittava varaus joko jatkuvana funktiona tulosignaaleista, tai approksimoimalla sitä muutamalla diskreetillä tasolla.Pipeline-tyyppisissä AD-muuntimissa peruslohko koostuu SC-kytketystä vahvistimesta, jonka kuormakapasitanssi on kytkettynä vahvistimen lähtöön asettumisen aikana. Tämän kapasitanssin esivaraaminen sopivasti tarjoaa hyvin yksinkertaisen keinon ohjata varausjakautumista niin, että vahvistimen tulossa oleva transientti saadaan minimoitua ja toiminta virtarajoitteisessa moodissa vältettyä. Tässäkin tapauksessa kehitettiin ja varmennettiin kaksi vaihtoehtoista toteutusta. Ensimmäisessä kuormakapasitanssin esivarausjännite lasketaan tulosuureiden jatkuvana funktiona erillisellä summausvahvistimella. Toisessa, hyvin minimalistisessa ratkaisussa esivaraukseen käytetään kolmea käytettävissä olevaa kiinteää jännitettä. Tämä menetelmä ei vaadi lainkaan ylimääräisiä aktiivikomponentteja.OsajulkaisutOsajulkaisut eivät sisälly väitöskirjan elektroniseen versioon.Sun, J., Rahkonen, T., & Neitola, M. (2012). Behavioral modeling of nonlinear settling for multiple cascaded SC stages. Proceeding of the IEEE NORCHIP Conference (NORCHIP’ 2012), Copenhagen, Denmark, 12-13 November 2012 (pp. 1-6). https://doi.org/10.1109/NORCHP.2012.6403136Sun, J., & Rahkonen, T. (2016). Solving the initial voltage of settling in switched-capacitor circuits. Proceeding of the IEEE International Instrumentation and Measurement Technology Conference (I2MTC’2016), Taipei, Taiwan, 23-26 May 2016 (pp. 1-4). https://doi.org/10.1109/I2MTC.2016.7520501Sun, J., & Rahkonen, T. (2018). Two capacitive-pulling techniques to aid the settling of SC residue amplifier. Proceeding of the IEEE International Instrumentation and Measurement Technology Conference (I2MTC’2018), Houston, Texas, USA, 14-17 May 2018 (pp. 1-4). https://doi.org/10.1109/I2MTC.2018.8409537Rinnakkaistallennettu versioSun, J., & Rahkonen, T. (2019). Speed up technique by pre-charging load capacitor in SC residue circuit. IEEE Transactions on Circuits and Systems, Express Briefs, 66(4), 522-526. https://doi.org/10.1109/TCSII.2018.2864596Rinnakkaistallennettu versioSun, J., & Rahkonen, T. (2019). Continuously controlled and discrete-level charge pumping techniques implemented in SC integrators. Analog Integrated Circuits and Signal Processing, 100(3), 653-661. https://doi.org/10.1007/s10470-019-01460-8Rinnakkaistallennettu versioAcademic dissertation to be presented, with the assent of the Doctoral Training Committee of Information Technology and Electrical Engineering of the University of Oulu, for public defence in the Wetteri auditorium (IT115), Linnanmaa, on 14 November 2019, at 12 noonAbstract
The goal of this dissertation was to study and model the settling transient response of switched-capacitor (SC) circuit, which is the most important building block of Analog-to-Digital converters (ADCs), and to improve the settling performance of the SC circuit implemented in ADC in CMOS technology.
In the design of the SC circuit, there are common obstacles in obtaining a precise and fast settling with low power consumption. The main contribution of this thesis is to speed up different SC circuits without adding extra power consumption or to achieve the required settling precision with low power consumption.
Two solutions to reduce the power consumption of SC integrators in sigma-delta (SD) ADCs were designed and verified by simulations. These implementations are based on the passive charge redistribution technique by injecting a precalculated open-loop charge in the output of the first integrator. The injected charge was implemented either by a continuous function of the input and feedback voltages or by quantizing to three levels. In both cases, the idea is to minimize the initial transient voltage in the input of the first OTA and hence bypass the slewing of the OTA.
Another approach was proposed for the traditional SC residue circuit of the pipeline ADC, where a load capacitor is connected to the output during the evaluation phase. Here, a pre-charge of the load capacitance can be used. One proposed implementation is called the continuously controlled pre-charged technique. It pre-charges the load capacitor to the proper voltage during the previous phase, connects the pre-charged load capacitor to the output of the OTA during the evaluation phase, and hence pulls the charge sharing so that the initial input step of the OTA is instantaneously minimized. The other implementation called the minimal pre-charged method implemented for the SC residue circuit of the pipeline ADC is to simply pre-charge the load capacitor with the fixed existing voltage, minimized the spread of the initial input voltage. This proposed technique did not require any additional active components.Tiivistelmä
Kytkettyihin kapasitansseihin (SC-tekniikka) perustuvat vahvistimet ovat CMOS-tekniikkaan perustuvien analogia-digitaalimuuntimien (AD-muunnin) tärkeimpiä osia. Tämän väitöstyön tavoitteena oli tutkia ja mallittaa SC-tekniikkaan perustuvien vahvistinpiirien asettumisaikaa, ja etsiä piiriteknisiä keinoja asettumisajan nopeuttamiseksi.
SC-piirien suunnittelun suurimpia ongelmia on saavuttaa tarkka ja nopea asettuminen mahdollisimman pienellä tehonkulutuksella. Tämän työn päätuloksina on joukko keinoja, joilla voidaan nopeuttaa SC-kytkettyjen vahvistimien asettumista ilman että niiden tehonkulutusta lisätään, tai saavuttaa aiempi suorituskyky pienemmällä tehonkulutuksella. Menetelmät perustuvat siihen, että SC-piirin passiivista varausjakautumista ohjataan niin, että vahvistimen tulosolmussa oleva transientti minimoituu, jolloin vahvistin ei ajaudu virtarajoitteiselle toiminta-alueelle, vaan sen asettuminen nopeutuu merkittävästi.
Sigma-delta-tyyppiset AD-muuntimet koostuvat SC-integraattoreista, ja näiden asettumisen nopeuttamiseen kehitettiin ja varmennettiin simuloiden kaksi tapaa. Varauksen jakautumista autettiin syöttämällä erillisellä varauspumpulla transkonduktanssivahvistimen lähtösolmuun tietty, integraattorin tilasta ja tuloista riippuva varaus. Tällöin vahvistimen tulossa näkyvä alkutransientti pienenee, ja vahvistin ei ajaudu virtarajoitteiselle toiminta-alueelleen, jolloin sen asettumisvirhe pienenee merkittävästi. Varausinjektio toteutettiin kahdella eri tavalla: laskemalla tarvittava varaus joko jatkuvana funktiona tulosignaaleista, tai approksimoimalla sitä muutamalla diskreetillä tasolla.
Pipeline-tyyppisissä AD-muuntimissa peruslohko koostuu SC-kytketystä vahvistimesta, jonka kuormakapasitanssi on kytkettynä vahvistimen lähtöön asettumisen aikana. Tämän kapasitanssin esivaraaminen sopivasti tarjoaa hyvin yksinkertaisen keinon ohjata varausjakautumista niin, että vahvistimen tulossa oleva transientti saadaan minimoitua ja toiminta virtarajoitteisessa moodissa vältettyä. Tässäkin tapauksessa kehitettiin ja varmennettiin kaksi vaihtoehtoista toteutusta. Ensimmäisessä kuormakapasitanssin esivarausjännite lasketaan tulosuureiden jatkuvana funktiona erillisellä summausvahvistimella. Toisessa, hyvin minimalistisessa ratkaisussa esivaraukseen käytetään kolmea käytettävissä olevaa kiinteää jännitettä. Tämä menetelmä ei vaadi lainkaan ylimääräisiä aktiivikomponentteja
A 1.2-V analog interface for a 300-MSps HD video digitizer in Core 65-nm CMOS
No full textAamir SA, Angelova P, Wikner JJ. A 1.2-V analog interface for a 300-MSps HD video digitizer in Core 65-nm CMOS. IEEE Transactions on VLSI Systems. 2014;22(4):888-898.This paper describes the front-end of a fully integrated analog interface for 300 MSps, high-definition video digitizers in a system on-chip environment. The analog interface is implemented in a 1.2 V, 65-nm digital CMOS process and the design minimizes the number of power domains using core transistors only. Each analog video receiver channel contains an integrated multiplexer with a current-mode dc-clamp, a programmable gain amplifier (PGA) and a pseudo second-order RC low-pass filter. The digital charge-pump clamp is integrated with low-voltage bootstrapped tee-switches inside the multiplexer, while restoring the dc component of ac-coupled inputs. The PGA contains a four-stage fully symmetric pseudo-differential amplifier with common-mode feedforward and inherent common-mode feedback, utilized in a closed loop capacitive feedback configuration. The amplifier features offset cancellation during the horizontal blanking. The video interface is evaluated using a unique test signal over a range of video formats for INL+/DNL+, INL-/DNL-. The 0.07-0.39 mV INL, 2-70 μV DNL, and 66-74 dB of SFDR, enable us to target various formats for 9-12 bit Low-voltage digitizers
Study and Simulation Example of a Redundant FIR Filter
No full textIn this paper we present a study and simulation results of the structure and design of a redundant finite-impulse response (FIR) filter. The filter has been selected as an illustrative example for biologically-inspired circuits, but the structure can be generalized to cover other signal processing systems. In the presented study, we elaborate on signal processing properties of the filter if we apply a redundant architecture were different computing paths can be utilized. An option is to utilize different computing paths as inspired by biological architectures (BIAs). We present typical simulation results for a low-pass filter illustrating the trade-offs and costs associated with this architecture
Supporting concurrent memory access in TCF-aware processor architectures
No full textThe Thick Control Flow (TCF) model packs together self-similar computations to simplify parallel programming and to eliminate redundant usage of associated software and hardware resources. While there are processor architectures supporting native execution ofprograms written for the model, none of them support concurrent memory access that can speed up execution of many algorithms by a logarithmic factor. In this paper, we propose an architectural solution implementing concurrent memory access for TCF-aware processors. The solution is based on bounded size step caches and two-phase structure of the TCF-aware processors. Step caches capture and hold the references made during the on-going step of an execution that are independent by the definition of TCF execution and therefore avoid coherence problems. The 2-phase structure reduces some concurrent accesses to a frontend operation followed by broadcast in the spreading network. According to our evaluation, a concurrent memory access-aware B-backend unit TCF processor executes certain algorithms up to B times faster than the baseline TCF processor
Design of a sampling switch for a 0.4-V SAR ADC using a multi-stage charge pump
No full textThis paper presents the design of a sampling switch to be used in the input interface to an ultra low-power 8-bit, 1-kS/s SAR ADC in 65 nm CMOS working at a supply voltage of 0.4 V. Important design trade-offs for the sampling switch in this low-voltage and low-power scenario are elaborated upon. The design of a multi-stage charge pump which generates the requisite boosted control voltage is described. A combination of the multi-stage charge pump and a leakage-reduced transmission-gate (TG) switch meets the speed requirement while mitigating leakage without employing additional voltages. Performance of the sampling switch has been characterized over process and temperature (PT) corners. In post-layout simulation, the sampling switch provides a linearity corresponding to 9.42 bits to 13.5 bits over PT corners with a worst-case power consumption of 216 pW while occupying an area of 25.4 μm × 24.7 μm.</p
Design of a reference voltage buffer for a 10-bit 50 MS/s SAR ADC in 65 nm CMOS
No full textThis paper presents the design of a fast-settling reference voltage buffer (RVBuffer) which is used to buffer the high reference voltage in a 10-bit, 50 MS/s successive approximation register (SAR) ADC implemented in 65 nm CMOS. Though numerous publications on SAR ADCs have appeared in recent years, the role of RVBuffers in ensuring ADC performance, the associated design challenges and impact on power and FoM of the entire ADC have not been discussed in-depth. In this work, the speed limitation on precise settling of the digital-to-analog converter voltage (DAC) in a SAR ADC imposed by parasitic inductances of the bondwire and PCB trace is explained. The crucial design parameters for the reference voltage buffer in the context of the SAR ADC are derived. Post-layout simulation results for the RVBuffer are provided to verify settling-time, noise and PSRR performance. In post-layout simulation which includes the entire pad frame and associated parasitics, the SAR ADC achieves an ENOB of 9.25 bits at a supply voltage of 1.2 V, typical process corner and sampling frequency of 50 MS/s for near-Nyquist input. Excluding the reference voltage buffer, the ADC consumes 697 ï¿œW and achieves an energy efficiency of 25 fJ/conversion-step while occupying a core area of 0.055 mm2.</p
Study of modified noise-shaper architectures for oversampled sigma-delta DACs
No full textIn this paper, modified low-complex, hybrid architectures for digital, oversampled sigma-delta digital-to-analog converters (ΣΔDACs) are explored in terms of signal-to-noise ratio (SNR) and subDAC complexity. The studied techniques illustrate the trade-off in terms of noise-shaper and DAC implementation complexity and loss in SNR. It is found that a fair amount of improvement in SNR is achieved by maintaining low-complexity of noise shaper. The complexity of the subDAC is yet a parameter, directly related to the number of output bits from the noise shaper. Two different architectures are investigated with respect to subDAC complexity and noise shaper complexity. It is shown that the required number of DAC unit elements (DUE) can be reduced to half.</p
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