1,720,965 research outputs found
Test and diagnosis of memories embedded in Automotive SoCs
Full text linkL'abstract è presente nell'allegato / the abstract is in the attachmen
A 6-bit Low-Area Hybrid ADC Design For System-on-Chip Measurements
Full text linkIn recent years, with the declining dimensions of transistors, the system-on-chips (SoCs) have had more physical defects. These physical defects ultimately result in failures that cannot be tolerated in functional safety applications such as electric cars, aerospace, etc. For the digital peripherals of the SoCs, there are well-known methods such as scan chains, whereas there are methods for analog circuits such as analog scan chains or Analog Test Bus (ATB).
This paper presents a 6-bit, low-area Analog-to-Digital Converter (ADC) for SoC analog voltage measurements. The advantage of the proposed ADC design is the low additional area cost to the design of the SoC and increasing the testability of the analog peripherals. This ADC design converts the analog signals, which are difficult to observe, to the digital domain, which is easy to route and observe. This architecture comprises two small ADCs for doing coarse and fine conversions. The ADC for the coarse conversion is a 3-bit SAR ADC, and the ADC for the fine conversion is a 3-bit flash ADC. The suggested ADC is implemented using the 130 nm technology of the Infineon, and it has a total area of 0.007 mm^2. The fine ADC of the proposed ADC can be shared between the peripherals nearby inside the SoC, and the additional area per peripheral would be only 0.0015 mm^2. The Signal-to-Noise Distortion Ratio (SNDR) of the design is 37dB, and the Figure of Merit (FoM) is 2.15 pJ/conv
A Novel Approach to Extract Embedded Memory Design Parameter Through Irradiation Test
Full text linkWith the capability improvements in modern Systemon-Chips (SoCs), the complexity of SoCs is increasing. Thus, manufacturers are investing heavily in designing and testing their devices. This complexity is causing a continuous expansion in the size of embedded memory structures. As a result of the shrinking dimensions of the transistors, memories are increasingly susceptible to Multiple Bit Upsets due to cosmic radiations.Testing memories requires more details about the internal hardware configurations. However, these details are not provided to the final customer, who is left with inexplicable effects.This paper proposes a new method to reconstruct architectural details from embedded SoC memories. This method extracts memory design parameters from Multiple Bit Upsets (MBUs) generated through a single irradiation test. The algorithm was tested on around 5,500 randomly generated memories. Each memory was injected with 100 Multiple Event Upsets (MEUs). The algorithm was set to test for each memory 20, 40, 60, 80, and 100 MEUs to validate the proposed approach. Alongside the correct memory design configuration (MDC), the algorithm found other possible MDCs. The quantity of these equivalent configurations decreased with the increment of the considered MEUs. This number decreased to an average of 2 equivalent MDCs when considering 100 MEUs
Low cost external serial interface watchdog for SoCs and FPGAs automatic characterization tests
Full text linkManufacturers must characterize their design deeply when designing and producing devices like FPGAs and SoCs. Information collected through simulation and physical experiments is the primary data source for manufacturers that can then decide the optimal working ranges of multiple critical parameters such as operating voltage, frequency, temperatures, etc. With complex devices such as SoCs, and FPGAs with integrated PLLs and voltage regulators, each combination of voltage and frequency can be checked by communicating the desired parameters to the DUT, running a functional test, and observing the results. However once the ATE sends the desired parameters to the DUT through SPI or other serial interfaces, the DUT may freeze and stop to accept new commands entirely. This is particularly problematic for targeted characterization that may include a minimal number of boards and DUTs and where the ATE may simply be a simple laptop without any automatic DUT reset capabilities. This paper presents an external serial communication watchdog designed using an ESP32-based board. Our watchdog can detect the communications coming from the ATE, monitor the answers from the DUT, and restart it through power cycling in case of freezing
ARBoard: Augmented Reality for PCB Operations in Industry 5.0
Full text linkIndustry 5.0 represents the next evolution in manufacturing, emphasizing human-centric approaches while lever-aging advanced technologies to create sustainable, resilient, and personalized production systems. Recent advancements in the Internet of Things, Cloud Computing, Machine Learning, Artificial Intelligence and Augmented Reality are starting to have significant effects in the manufacturing lifecycle thanks to the increase in the efficiency and productivity through automation and optimization while maintaining human expertise at the center of operations. Focusing on the electronic manufacturing world, these per-vasive new technologies continue to improve, and together with automation play a fundamental role in today's industrial pro-duction. Nevertheless, manual activities remain essential in the development lifecycle of electronic products and of their PCBs. Manual labor is necessary especially during the prototyping phase to debug the design and validate its correct behavior. For this purpose, test engineers have to constantly switch between PCB schematic and layout files in a process that is slow, error-prone and stressful. The inefficiency of this process leads to a bigger time-to-market and a cost increase as well as potentially impacting the final quality of the products. This paper presents ARBoard, an innovative smart glasses-ready Augmented Reality (AR) application to bring manual PCB operations to the Industry 5.0 era. In AR, the user visualizes useful information about the board under test such as datasheet, schematic and markers projected on the physical board. The markers are placed by the user that directly points at the schematics and chooses the components that they want to locate on the board. This feature eliminates the need for cross-referencing between multiple documents and the successive localization of the components on the physical board. The functionalities of the app are expanded by a local and private AI assistant. Users can ask questions about the board, and the AI assistant will answer taking information from the board's datasheet. The AI assistant also automatically highlights the relevant component as it answers to the user
Density-oriented diagnostic data compression strategy for characterization of embedded memories in Automotive Systems-on-Chip
Full text linkEmbedded System-on-Chip (SoC) memory requirements in the Automotive industry are constantly growing. For this reason, memories occupy a significant part of Automotive SoC's die area, increasing the defect probability inside the embedded storage. Automotive SoC manufacturers need to deeply test their embedded memories as they are one of the significant contributors to the yield of their devices.
The test effort increases for the characterization of new technologies and new families of devices that need to be characterized by the manufacturers. These tests generate a massive quantity of diagnostic information that is incredibly valuable for designers and technology experts.
This diagnostic information can be analyzed to identify and correct possible weaknesses and misbehavior. The easiest way to collect memory diagnostic information consists of failure bitmaps in which each fault is saved as coordinates. This method is the simplest solution to implement. However, logging the coordinates of every fault may generate an unmanageable quantity of data. This problem is exacerbated when there is an on-chip limitation on the amount of data that can be saved or transmitted to the external world.
This paper presents an optimized on-chip compression algorithm that allows to reduce the required on-chip memory to store diagnostic information during embedded memory testing. This solution allows the reconstruction of a failure bitmap, generating a topological representation of the density of the failings bits in the embedded on-chip memory. The proposed approach effectively reduces the used storage to a fraction with respect to the one used by the original failing bitmap. The algorithm uses a coordinates-based approach, in which the memory is logically divided into equally divided sectors. The small time overhead introduced by the algorithm is compensated by the ability to achieve optimal space utilization
Going Beyond Counting First Authors in Author Co-citation Analysis
Full text linkThe present study examines one of the fundamental aspects of author co-citation analysis (ACA) - the way co-citation
counts are defined. Co-citation counting provides the data on which all subsequent statistical analyses and mappings
are based, and we compare ACA results based on two different types of co-citation counting - the traditional type that
only counts the first one among a cited work's authors on the one hand and a non-traditional type that takes into
account the first 5 authors of a cited work on the other hand. Results indicate that the picture produced through this non-traditional author co-citation counting contains more coherent author groups and is therefore considerably clearer. However, this picture represents fewer specialties in the research field being studied than that produced through the traditional first-author co-citation counting when the same number of top-ranked authors is selected and analyzed. Reasons for these effects are discussed
A Versatile Strategy for Comprehensive Data Collection and Retention in Embedded SoC Memories
Full text linkIn modern automotive system-on-chip (SoC) designs, large embedded flash memories have become a standard feature. Since they occupy a significant percentage of the die area, their impact on the SoCs’ overall yield is substantial, making them a critical component in the production process. Embedded memories are then deeply tested to unsure their reliability. The data collected through these tests are fundamental to chip designers and test engineers to iron out their designs and understand the most common failure mechanisms. A common approach for data collection is the generation of bitmaps based on the gathering of individual fail coordinates in a list-based fashion. Other more efficient compaction or compression approaches exist and all these approaches can use dedicated internal memories to store the result of a given test. Unfortunately, all the methods currently found in the literature do not allow diagnostic data retention along multiple tests, requiring constant and time-consuming communications with the external tester, increasing the test cost for the manufacturers.
This article presents an on-chip algorithm to compact and retain diagnostic information from multi-step embedded memories testing. The foundation of this work lies in an efficient shape recognition and encoding algorithm. The collected information is stored in a dedicated nonvolatile on-chip memory. Information about the tests that generated a given set of fault shapes is also encoded in this dedicated diagnostic memory, enabling manufacturers to collect all the diagnostic information at the end of their test flow. Experimental results on over 110 Automotive SoCs made by InfineonTM show that using the proposed approach, 100% of the diagnostic information of devices undergoing a standard automotive-grade test flow is permanently encodable in a limited 24 KB diagnostic space while also consistently reducing the total test time of up to 53.8% with respect to traditional list-based approaches
Variations on the Author
Full text link“Variations on the Author” discusses two of Eduardo Coutinho’s recent films (Um Dia na Vida, from 2010, and Últimas Conversas, posthumously released in 2015) and their contribution to the general question of documentary authorship. The director’s filmography is characterized by a consistent yet self-effacing form of authorial self-inscription: Coutinho often features as an interviewer that rather than express opinions propels discourses; an interviewer that is good at listening. This mode of self-inscription characterizes him as an author who is not expressive but who is nonetheless markedly present on the screen. In Um Dia na Vida, however, Coutinho is completely absent form the image, while Últimas Conversas, on the contrary, includes a confessional prologue that moves the director from the margins to the center of his films. This article examines the ways in which these works stand out in the filmography of a director who offers new insights into the notion of cinematic authorship
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