1,720,962 research outputs found
Design space exploration for a Local Object Store
No full textNowadays, modern Integrated Circuit (IC) technology allows processor manufacturers to produce complex designs with up to a few billions of transistors.Technology limitations and the end of voltage and frequency scaling forced computer architecture to multicore designs and more specialized solutions on hardware. These technology trends increased memory bandwidth pressure, exposing modern computer systems to bandwidth limitations. Therefore, a large and increasing fraction of the area is occupied to efficiently manage the available memory bandwidth, especially the off-chip bandwidth. In addition, the failure of Dennard Scaling along with the end of multicore scaling gave rise to the Dark Silicon era, in which the percentage of transistors in an IC that can be simultaneously powered-on is decreasing. Thus, under a fixed power and thermal budget, decreasing the main memory accesses of a processor relieves operational costs and rises the potential for increased computing performance. In order to tackle this problem, we investigate the possibilities to offload functionalities of the software to hardware due to the drop in the cost of hardware. Based on our observations on modern programming languages, we formulate the hypothesis that object caching presents potential to advance the main processor's functionalities in handling objects which are the most commonly used memory structure in modern languages. After formulating the concept of a Local Object Store (LOS), this master thesis presents our progress on developing the framework for our proof of concept. A LOS is expected to decrease the number of main memory references by leveraging the "infant mortality" property of objects in real-life applications. Our proposed design provides support for the basic object manipulation operations while maintaining reference counters for the local objects.Therefore, comparing LOS with a cache memory, it permits the construction and destruction of short-lived objects without polluting the rest of the memory hierarchy. Our framework consists of a Smart Pointer library, two modified tracing tools that allow us to obtain traces from microbenchmarks, and a basic simulator for a Cache-LOS memory unit. Moreover, we develop and trace 3 microbenchmarks and using our framework simulate a 39% average reduction in the main memory accesses for a Cache-LOS memory architecture compared to a cache-only memory configuration. These promising results show the benefits of an integrated Cache-LOS to manipulate object structures.Computer EngineeringMicroelectronics & Computer EngineeringElectrical Engineering, Mathematics and Computer Scienc
Feeding High-Bandwidth Streaming-Based FPGA Accelerators
No full textA new class of accelerator interfaces has signi cant implications on system architecture. An order of magnitude more bandwidth forces us to reconsider FPGA design. OpenCAPI is a new interconnect standard that enables attaching FPGAs coherently to a high-bandwidth, low- latency interface. Keeping up with this bandwidth poses new challenges for the design of accelerators, and the logic feeding them.This thesis is conducted as part of a group project, where three other master students investigate database operator accelerators. This thesis focuses on the logic to feed the accelerators, by designing a recon gurable multi-stream bu er architecture. By generalizing across multiple common streaming-like accelerator access patterns, an interface consisting of multiple read ports with a smaller than cache line granularity is desired. At the same time, multiple read ports are allowed to request any stream, including reading across a cache line boundary.The proposed architecture exploits di erent memory primitives available on the latest genera- tion of Xilinx FPGAs. By combining a traditional multi-read port approach for data duplication with a second level of bu ering, a hierarchy typically found in caches, an architecture is pro- posed which can supply data from 64 streams to eight read ports without any access pattern restrictions.A correct-by-construction design methodology was used to simplify the validation of the design and to speedup the implementation phase. At the same time, the design methodology is doc- umented and examples are provided for ease of adoption. With the design methodology, the proposed architecture has been implemented and is accompanied by a validation framework.Various con gurations of the multi-stream bu er have been tested. Con gurations up to 64 streams with four read ports meet timing with an AFU request-to-response latency of ve cycles. The largest con guration with 64 streams and eight read ports fails timing. Limiting factors are the inherent architecture of FPGAs, where memories are physically located in speci c columns. This makes extracting data complex, especially at the target frequencies of 200 MHz and 400 MHz. Wires are scattered across the FPGA and wire delay becomes dominant.FPGA design at increasing bandwidths requires new design approaches. Synthesis results are no guarantee for the implemented design, and depending on the design size, could indicate a very optimistic operating frequency. Therefore, designing accelerators to keep up with an order of magnitude more bandwidth compared to the current state-of-the-art is complex, and requires carefully thought out accelerator cores, combined with an interface capable of feeding it.ISBN 978-94-6186-886-2Computer Engineerin
A Resiliency-First Approach to Distributed DAG Computations
No full textA framework is introduced for computations with transformations on immutable data. Inspiration is taken from Apache Spark, however the model of computation is generalized from an emphasis on narrow and wide dependencies, to an arbitrary set of transformations that form a directed acyclic graph (DAG). A distributed scheduling algorithm is developed with resiliency mechanisms that can account for stopping failure. Furthermore some properties of the system are derived. Finally future work is discussed showing there is fertile ground for further research and development to extend this work.Computer Engineerin
Going Beyond Counting First Authors in Author Co-citation Analysis
Get PDFThe present study examines one of the fundamental aspects of author co-citation analysis (ACA) - the way co-citation
counts are defined. Co-citation counting provides the data on which all subsequent statistical analyses and mappings
are based, and we compare ACA results based on two different types of co-citation counting - the traditional type that
only counts the first one among a cited work's authors on the one hand and a non-traditional type that takes into
account the first 5 authors of a cited work on the other hand. Results indicate that the picture produced through this non-traditional author co-citation counting contains more coherent author groups and is therefore considerably clearer. However, this picture represents fewer specialties in the research field being studied than that produced through the traditional first-author co-citation counting when the same number of top-ranked authors is selected and analyzed. Reasons for these effects are discussed
Variations on the Author
Get PDF“Variations on the Author” discusses two of Eduardo Coutinho’s recent films (Um Dia na Vida, from 2010, and Últimas Conversas, posthumously released in 2015) and their contribution to the general question of documentary authorship. The director’s filmography is characterized by a consistent yet self-effacing form of authorial self-inscription: Coutinho often features as an interviewer that rather than express opinions propels discourses; an interviewer that is good at listening. This mode of self-inscription characterizes him as an author who is not expressive but who is nonetheless markedly present on the screen. In Um Dia na Vida, however, Coutinho is completely absent form the image, while Últimas Conversas, on the contrary, includes a confessional prologue that moves the director from the margins to the center of his films. This article examines the ways in which these works stand out in the filmography of a director who offers new insights into the notion of cinematic authorship
Appropriate Similarity Measures for Author Cocitation Analysis
Get PDFWe provide a number of new insights into the methodological discussion about author cocitation analysis. We first argue that the use of the Pearson correlation for measuring the similarity between authors’ cocitation profiles is not very satisfactory. We then discuss what kind of similarity measures may be used as an alternative to the Pearson correlation. We consider three similarity measures in particular. One is the well-known cosine. The other two similarity measures have not been used before in the bibliometric literature. Finally, we show by means of an example that our findings have a high practical relevance.information science;Pearson correlation;cosine;similarity measure;author cocitation analysis
Dispelling the Myths Behind First-author Citation Counts
Get PDFWe conducted a full-scale evaluative citation analysis study of scholars in the XML research field to explore just how different from each other author rankings resulting from different citation counting methods actually are, and to demonstrate the capability of emerging data and tools on the Web in supporting more realistic citation counting methods. Our results contest some common arguments for the continued
use of first-author citation counts in the evaluation of scholars, such as high correlations between author rankings by first-author citation counts and other citation
counting methods, and high costs of using more realistic citation counting methods that are not well-supported by the ISI databases. It is argued that increasingly available digital full text research papers make it possible for citation analysis studies to go beyond what the ISI databases have directly supported and to employ more
sophisticated methods
FPGA-Based High Throughput Merge Sorter
No full textAs database systems have shifted from disk-based to in-memory, and the scale of the database in big data analysis increases significantly, the workloads analyzing huge datasets are growing. Adopting FPGAs as hardware accelerators improves the flexibility, parallelism and power consumption versus CPU-only systems. The accelerators are also required to keep up with high memory bandwidth provided by advanced memory technologies and new interconnect interfaces. Sorting is the most fundamental database operation. In multiple-pass merge sorting, the final pass of the merge operation requires significant throughput performance to keep up with the high memory bandwidth. We study the state-of-the-art hardware-based sorters and present an analysis of our own design. In this thesis, we present an FPGA-based odd-even merge sorter which features throughput of 27.18 GB/s when merging 4 streams. Our design also presents stable throughput performance when the number of input streams is increased due to its high degree of parallelism. Thanks to such a generic design, the odd-even merge sorter does not suffer throughput drop for skewed data distributions and presents constant performance over various kinds of input distributions.Electrical Engineering | Microelectronic
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