1,721,603 research outputs found
Kwon, Han-Joon
No full text학위논문(박사)--아주대학교 일반대학원 :전자공학과,2009. 8고속도로 자동요금지불시스템(ETCS)인 하이패스시스템은 단거리 무선통신기술인 능동IR, RF기술을 활용하여 전국 고속도로 영업소 등에서 운영 중에 있다.
본 논문에서는 이러한 하이패스시스템에 적용된 단거리 무선통신기술 중 5.8GHz 대역의 능동RF 기술을 활용하여, 기존에 보급된 차량단말기로부터 구간교통정보를 수집․가공하고 실시간으로 변화하는 교통상황 파악이 가능하도록 연속류인 고속도로 환경에 적합한 DSRC기반의 교통정보처리시스템을 연구 개발하였다.
먼저, 국내외 ITS 분야에 적용된 DSRC 및 무선통신기술을 고찰하고, DSRC 기술에 기반을 둔 미국의 E-ZPass 등 다양한 기술이 적용되어 운영중인 교통정보시스템을 분석하여 구간검지체계를 통한 교통정보 정확도 향상을 위한 시스템 요구사항 및 개발방향을 정립하였다.
DSRC 기술이 적용된 하이패스 기반 교통정보처리시스템을 개발하기 위해서 고속도로 본선의 환경조건을 고려하였으며, 하이패스 차량단말기를 장착한 개별차량의 통과시각을 기준으로 구간 통행속도 및 통행시간 생성을 기본 기능으로 설정하였고 향후 차량단말기에 교통정보제공이 가능하고, IR 통신방식을 수용이 가능하도록 고려하였다.
시스템 개발과정에서는 DSRC 교통정보처리시스템 측면과 운영자 측면에 따라 요구기능을 정의하고, 정보교환을 위한 논리 아키텍쳐와 시스템 구성을 위한 물리 아키텍처를 제시하여 전체적인 시스템을 구성하였다.
DSRC 교통정보처리시스템은 응용 인터페이스와 하드웨어로 분류하였으며, 응용 인터페이스에서는 기존의 자동요금지불 응용 인터페이스를 참조하여 통신 유닛의 기능, 노변기지국의 소프트웨어 구성과 각 장치간 교환되는 정보항목 및 정보형식 등을 정의하였으며, 노변기지국과 교통정보 서버간 통신 프로토콜을 포함하였다.
하드웨어에서는 외관 및 내부구성을 포함한 각 하드웨어 장치의 구성과 구성부를 이루는 모듈에 대한 하드웨어 접속 규격을 제시하였다.
노변기지국에서 수집된 데이터는 교통정보 서버에서 교통정보로서 제공하기 위한 형태로 가공하는 과정이 필요하였으며, 이를 위해 수집된 데이터를 실제 교통상황을 대표할 수 있도록 이상치 제거, 결측 보정, 평활화 기법을 적용하는 알고리즘을 도출하였다.
교통정보 가공 알고리즘은 수집한 데이터의 상․하위 5%씩 제거 후 이상치를 판단한다. 이후 문제가 없다면 대푯값을 통해 평균통행시간을 산출한 후 구간 통행속도를 계산하며 이 데이터에서 돌발상황을 확인하거나 소통상태가 원활한지를 판단한다. 마지막으로 통행시간당 속도를 판별하여 정보제공구간의 정체를 판단한다.
시스템 개발 후, DSRC 교통정보처리시스템의 기술적 특성분석과 검증을 위하여 고속도로와 유사한 시험도로 환경인 여주 폐도에서 통신영역 및 통신특성, 정보 정확도와 안테나 구성방안에 대한 시험측정을 하였다.
하나의 안테나에서 다차로 통신영역을 설정하여 지점정보(지점속도)를 생성한 결과 RF 기술의 경우 차로별 정확한 통신영역의 길이가 다르고, 주행차량의 차로구분이 안 되는 특성으로 인하여 고속주행 시 실제 통과속도와 30% 이상의 오차가 발생하여 지점정보 정확도가 낮은 것으로 분석되었으나, 통신성공률은 95% 이상으로 매우 양호한 것으로 보여주었다.
실 도로환경에서의 현장적용과 기술검증을 위하여 경부고속도로의 서울-수원 상행구간에 시스템을 설치하여, 실제 고속도로 주행환경 하에서의 교통정보 수집 및 가공에 대한 시험을 수행하였다. 시험을 통하여 수집된 자료와 고속도로 검지기에서 수집된 구간 교통정보를 비교 분석한 결과, 지․정체 발생 시 구간별로 기존의 검지기보다 10% 이상의 절대평균 오차비율(MAPE)이 감소하는 것으로 나타났으며, 돌발상황 검지의 경우 약 40~60분 빠르게 검지하는 것으로 분석되었다.
본 연구에서 개발된 하이패스 기반의 DSRC 교통정보처리시스템은 기존의 지점검지 기반의 교통정보시스템에서 발생하는 오차를 감소시키고, 보다 빠르게 돌발상황을 검지할 수 있는 것으로 분석되었으며, 특히 차량단말기를 이용한 교통정보 제공 등 보다 다양하고 수준 높은 ITS 서비스 분야에 적용이 가능할 것으로 판단된다.제 1 장 서론
제 2 장 이론적 고찰
제 1 절 교통정보 수집장치 구성
제 2 절 교통정보처리시스템 가공 알고리즘 연구
제 3 절 근거리 무선통신 프로토콜의 표준
제 4 절 국내․외 DSRC 관련연구
제 3 장 DSRC 교통정보처리시스템 설계
제 1 절 교통정보처리시스템 요구기능
제 2 절 DSRC 교통정보처리시스템 아키텍쳐 정의
제 3 절 시스템 기능별 설계
제 4 절 DSRC 교통정보처리시스템 H/W 설계
제 5 절 DSRC 교통정보처리시스템 S/W 설계
제 6 절 DSRC 교통정보처리 알고리즘
제 4 장 DSRC 교통정보처리시스템 시험성능평가
제 1 절 시험도로환경에서의 성능평가
제 2 절 실 도로환경에서의 성능평가
제 5 장 결론Maste
Reliable Oscillatory Neural Network Utilizing a Thermally Stable Single Transistor-based Oscillator
No full textA reliable oscillatory neural network (ONN) is demonstrated using a thermally stable single transistorbased oscillator (1T-oscillator). Instead of relying on thermally sensitive impact ionization (I.I.), thermally insensitive band-to-band tunneling (BTBT) is utilized to trigger a single-transistor latch (STL), ensuring stable oscillation characteristics. The study investigates the properties of coupled oscillators, the fundamental elements of ONN, across different temperature settings to confirm thermal stability effects. Additionally, the reliability of ONN is verified through a vertex coloring task, a representative problem in nondeterministic polynomial time hard (NP-hard) combinatorial optimization.N
Power reduction for recovery of a FinFET by electrothermal annealing
No full textA strategy of reducing the power consumption to cure gate dielectric damage by electrothermal annealing (ETA) is proposed. A tri-gate FinFET was fabricated to demonstrate the damage curing by the ETA. Localized Joule heat induced by high current flowing through dual gate electrodes successfully annealed the damaged gate dielectric. Furthermore, a design methodology to save power consumption during the ETA was explored. Electrical measurements and simulations were performed considering scaling-down and material engineering points of view. This work contributes to improving the reliability of the FinFET by developing the ETA approach with reduced power consumption.N
Mimicking biological synaptic plasticity with a leaky charge-trap FinFET
No full textProposed future computing systems may be based on electronic devices which mimic the synaptic plasticity of biological brains. Even though various electronic devices have been proposed to emulate synaptic functions, to date scalability, large-scale integration, productivity, and co-integration with control circuits in a single chip have not been achieved. This work demonstrates a highly scalable and 3-dimensional (3-D) structured leaky charge-trap (LCT) fin-shaped field effect transistor (FinFET) fabricated using 100% Complementary Metal-Oxide-Semiconductor (CMOS) compatible materials and processes. This LCT-FinFET emulated synaptic plasticity with a post-synaptic current (PSC), which is analogous to the post-synaptic potential (PSP) observed in biological synapses. In addition, various synaptic functions used to strengthen all five representative types of synaptic plasticity, spike-amplitude dependent plasticity (SADP), spike-duration dependent plasticity (SDDP), spike-frequency dependent plasticity (SFDP), spike-number dependent plasticity (SNDP), and spike-timing-dependent plasticity (STDP), were artificially mimicked using paired-pulse facilitation (PPF) in the LCT-FinFET. Similar to the physiological processes of memorizing and forgetting in the human brain, short-term memory (STM) devices resulting from inherent leaky gate dielectrics of the LCT-FinFET were reinforced to form long-term memory (LTM) devices by rehearsing pre-synaptic spikes.N
Multiparametric MRI and 18F-FDG PET features for differentiating gastrointestinal stromal tumors from benign gastric subepithelial lesions
No full textObjectives To investigate whether multiparametric magnetic resonance imaging (MRI) and F-18-fluorodeoxyglucose positron emission tomography (PET) can be helpful in differentiating gastrointestinal stromal tumors (GISTs) from non-GISTs and high-risk GISTs from low-risk GISTs. Methods This retrospective study included 56 patients with pathologically confirmed GISTs (n = 39), leiomyoma (n = 8), schwannoma (n = 5), heterotopic pancreas (n = 3), and glomus tumor (n = 1) who underwent MRI and/or PET examinations. Two radiologists reviewed MRI regarding location, shape, contour, growth pattern, margin, signal intensity (SI) on T1- (T1WI) and T2-weighted images (T2WI), degree and pattern of enhancement, hemorrhage, and necrosis. Mean apparent diffusion coefficient (ADC) and maximum standardized uptake value (SUVmax) were measured. Imaging features were compared among non-GISTs, low-risk GISTs, and high-risk GISTs using uni- and multivariate statistical analyses. Results Size, longitudinal location, shape, contour, growth pattern, SI on T1- and T2WI, enhancement pattern, hemorrhage, necrosis, ADC, and SUVmax were significantly different among non-GISTs, low-risk GISTs, and high-risk GISTs (p < 0.05). On multivariate analysis, SI on T2WI (hazard ratio [HR], 66.0; p = 0.002) was the only independent variable for differentiating GISTs from non-GISTs whereas enhancement pattern (HR, 56.0; p = 0.041), ADC (HR, 0.997; p = 0.01), and SUVmax (HR, 2.08; p = 0.027) were significant features for differentiating between high-risk and low-risk GISTs. Conclusions Several qualitative and quantitative MRI and PET features including ADC and SUVmax values are significantly different among non-GISTs, low-risk GISTs, and high-risk GISTs. Multiparametric information obtained from MRI with or without PET can be useful for differentiation of gastric subepithelial tumors as well as for determining patients' management and prognosis.N
A Nanoscale Bistable Resistor for an Oscillatory Neural Network
No full textCoupled oscillators construct an oscillatory neural network (ONN) by mimicking the interactions among neurons in the human brain. This work demonstrates a fully CMOS-based oscillator consisting of a bistable resistor (biristor), which shares a structure identical with that of a metal-oxide-semiconductor field-effect transistor, except for the use of a gate electrode. The biristor-based oscillator (birillator) generates oscillating voltage signals in the form of spikes due to a single transistor latch phenomenon. When two birillators are connected with a coupling capacitor, they become synchronized with a phase difference of 180 degrees. These coupled oscillation characteristics are experimentally investigated for an ONN. As practical applications of the ONN with coupled birillators, edge detection and vertex coloring are conducted by encoding information into phase differences between them. The proposed fully CMOS-based birillators are advantageous for low power consumption, high CMOS compatibility, and a compact footprint area.N
Highly durable and energy-efficient probabilistic bits based on h-BN/SnS2 interface for integer factorization
No full textAs social networks and related data processes have grown exponentially in complexity, the efficient resolution of combinatorial optimization problems has become increasingly crucial. Recent advancements in probabilistic computing approaches have demonstrated significant potential for addressing these problems more efficiently than conventional deterministic computing methods. In this study, we demonstrate a highly durable probabilistic bit (p-bit) device utilizing two-dimensional materials, specifically hexagonal boron nitride (h-BN) and tin disulfide (SnS2 ) nanosheets. By leveraging the inherently stochastic nature of electron trapping and detrapping at the h-BN/SnS2 interface, the device achieves durable probabilistic fluctuations over 108 cycles with minimal energy consumption. To mitigate the static power consumption, we integrated an active switch in series with a p-bit device, replacing conventional resistors. Furthermore, employing the pulse width as the control variable for probabilistic switching significantly enhances noise immunity. We demonstrate the practical application of the proposed p-bit device in implementing invertible Boolean logic gates and subsequent integer factorization, highlighting its potential for solving complex combinatorial optimization problems and extending its applicability to real-world scenarios such as cryptographic systems. imageY
One Biristor-Two Transistor (1B2T) Neuron With Reduced Output Voltage and Pulsewidth for Energy-Efficient Neuromorphic Hardware
No full textA highly scalable neuron composed of one biristor and two transistors (1B2T neuron) is proposed. The output voltage and pulsewidth in the 1B2T neuron are reduced compared with that in the previously reported one biristor (1B) neuron solely. The approach can greatly enhance the energy efficiency of the neuromorphic hardware by decreasing the energy consumption. To demonstrate the 1B2T neuron, SPICE simulations of 1B2T were performed, reflecting the measured spiking property of the fabricated 1B. The output voltage and the energy consumption were analyzed under various conditions of two transistors (2T) such as threshold voltage and applied voltage. In addition to reducing the energy consumption of the neuromorphic hardware, the output voltage of the 1B2T neuron is adjustable, by controlling the applied voltage to the neuron.N
Data Sanitization of SRAM by Thermal Distortion
No full textThermal distortion of a memory state is demonstrated for data sanitization of static random access memory (SRAM). Data stored in SRAM are believed to be deleted when power is turned off. However, it has been reported that the data can remain for a certain time even in powered- OFF SRAM, especially in a low-temperature environment. When a cold boot attack is attempted at low temperature, the stored data in SRAM are secured by thermal distortion at induced high temperature. For an experimental demonstration of data sanitization, heat is intentionally applied to a commercial SRAM chip, which is connected with a Raspberry pi board to write and read data. Supportive circuit and thermal simulations are performed to analyze electrical and thermal characteristics during heat treatment.N
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