1,720,970 research outputs found
Reduction of Gate-Induced Drain Leakage (GIDL) Current in Single-Gate Ultra-Thin Body and Double-Gate FinFET Devices
No full textTunable Work Function Molybdenum Gate Technology for FDSOI-CMOS
No full textSupport from SRC-MARCO under contract 2001-MT-887 and the UC Berkeley Microfabrication Laboratory is grateffly acknowledged
Ultra-Thin Body Silicon- on-Insulator (UTB SOI) MOSFET with Metal Gate Work-Function Engineering for Sub-70nm Technology Node
No full text
Going Beyond Counting First Authors in Author Co-citation Analysis
Full text linkThe present study examines one of the fundamental aspects of author co-citation analysis (ACA) - the way co-citation
counts are defined. Co-citation counting provides the data on which all subsequent statistical analyses and mappings
are based, and we compare ACA results based on two different types of co-citation counting - the traditional type that
only counts the first one among a cited work's authors on the one hand and a non-traditional type that takes into
account the first 5 authors of a cited work on the other hand. Results indicate that the picture produced through this non-traditional author co-citation counting contains more coherent author groups and is therefore considerably clearer. However, this picture represents fewer specialties in the research field being studied than that produced through the traditional first-author co-citation counting when the same number of top-ranked authors is selected and analyzed. Reasons for these effects are discussed
Sub-20nm CMOS FinFET Technologies
No full textThe authors would like to thank the University of California-Berkeley Microlab stafs for their supports in device fabrication. This research was sponsored by SRC under Contract 2000-NJ-850 and MARCo contract 2001-MT-88
Experimental Analysis and Mathematical Modeling of Program Efficiency in Gate-Side Injection Type FeFETs Depending on the Gate Interlayer
No full textWe experimentally analyze the incremental step pulse programming (ISPP) characteristics of gate-side injection type MIFIS FeFETs, which feature a metal - gate interlayer (G.IL) - ferroelectrics - channel interlayer (Ch.IL) - Si stack, with a focus on the role of the G.IL. We also propose a mathematical model considering ferroelectric (FE) switching behavior. MIFIS FeFETs have recently garnered attention due to their ability to achieve lower program (PGM) voltages and wider memory windows (MWs) compared to typical channel-side injection type charge trap flash (CTF) devices, thanks to the injection of charges (Q(it)') from the gate and polarization switching dynamics. However, guidelines on the influence of the G.IL on ISPP characteristics and endurance, critical for NAND cell, are lacking. Here, we experimentally investigate the impact of the G.IL on the ISPP slope of MIFIS FeFETs and, through mathematical modeling, propose a G.IL design to optimize MIFIS FeFET performance. Furthermore, we analyze the degradation of endurance characteristics depending on the type of G.IL, suggesting that the excessive Q(it) injected from the Ch.IL, together with polarization pinning, contributes to overall endurance degradation. Lastly, we demonstrate that by utilizing a low-kappa SiO2 G.IL (6 nm), a MW of 6.5 V and an ISPP slope greater than 3 can be achieved. Our MIFIS FeFET also exhibits disturbance immunity even at voltages exceeding 14 V, which is critical in preventing V-th shifts during various disturbances. Our research and model can provide valuable guidelines for the study of gate-injection type FeFET, which are actively being explored as next-generation NAND Flash memory technologies.
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