1,721,315 research outputs found
CIRCA-GPUs: Increasing instruction reuse through inexact computing in GP-GPUs
No full text"Inexact computing" provides an opportunity for exploiting application characteristics to improve energy efficiency. This is particularly true of error-tolerant image processing applications that are often implemented using large scale parallel processing resources in general-purpose graphics processing units or GP-GPUs. GP-GPUs provide fine-grained parallel architecture by integrating a large number of relatively small and tightlycoupled processing cores. We propose CIRCA-GPUs, a method to jointly exploit fine-grained parallelism and inexact computing in GP-GPUs by reusing results of instructions across different cores and over time. This spatiotemporal instruction reuse with systematic approximation of computing results increases the rate of reuse to improve energy efficiency
Variability Mitigation in Nanometer CMOS Integrated Systems: A Survey of Techniques from Circuits to Software
No full textVariation in performance and power across manufactured parts and their operating conditions is an accepted reality in modern microelectronic manufacturing processes with geometries in nanometer scales. This article surveys challenges and opportunities in identifying variations, their effects and methods to combat these variations for improved microelectronic devices. We focus on computing devices and their design at various levels to combat variability. First, we provide a review of key concepts with particular emphasis on timing errors caused by various variability sources. We consider methods to predict and prevent, detect and correct, and finally conditions under which such errors can be accepted; we also consider their implications on cost, performance and quality. We provide a comparative evaluation of methods for deployment across various layers of the system from circuits, architecture, to application software. These can be combined in various ways to achieve specific goals related to observability and controllability of the variability effects, providing means to achieve cross-layer or hybrid resilience. We then provide examples of real world resilient single-core and parallel architectures. We find that parallel architectures and parallelism in general provide the best means to combat and exploit variability to design resilient and efficient systems. Using programmable accelerator architectures such as clustered processing elements and GP-GPUs, we show how system designers can coordinate propagation of timing error information and its effects along with new techniques for memoization (i.e., spatial or temporal reuse of computation). This discussion naturally leads to use of these techniques into emerging area of "approximate computing," and how these can be used in building resilient and efficient computing systems. We conclude with an outlook for the emerging field
From variability tolerance to approximate computing in parallel integrated architectures and accelerators
No full textThis book focuses on computing devices and their design at various levels to combat variability. The authors provide a review of key concepts with particular emphasis on timing errors caused by various variability sources. They discuss methods to predict and prevent, detect and correct, and finally conditions under which such errors can be accepted; they also consider their implications on cost, performance and quality. Coverage includes a comparative evaluation of methods for deployment across various layers of the system from circuits, architecture, to application software. These can be combined in various ways to achieve specific goals related to observability and controllability of the variability effects, providing means to achieve cross layer or hybrid resilience. · Covers challenges and opportunities in identifying microelectronic variability and the resulting errors at various layers in the system abstraction; · Enables readers to assess how various levels of circuit and system design can mitigate the effects of variability; · Demonstrates overall system architecture of what is now called “approximate computing” paradigm in massively parallel integrated architectures and accelerators
Improving resilience to timing errors by exposing variability effects to software in tightly-coupled processor clusters
No full textManufacturing and environmental variations cause
timing errors in microelectronic processors that are typically
avoided by ultra-conservative multi-corner design margins or
corrected by error detection and recovery mechanisms at the
circuit-level. In contrast, we present here runtime software support
for cost-effective countermeasures against hardware timing
failures during system operation. We propose a variability-aware
OpenMP (VOMP) programming environment, suitable for
tightly-coupled shared memory processor clusters, that relies
upon modeling across the hardware/software interface. VOMP is
implemented as an extension to the OpenMP v3.0 programming
model that covers various parallel constructs, including ,
, and . Using the notion of work-unit vulnerability
(WUV) proposed here, we capture timing errors caused by
circuit-level variability as high-level software knowledge. WUV
consists of descriptive metadata to characterize the impact of variability
on different work-unit types running on various cores. As
such, WUV provides a useful abstraction of hardware variability
to efficiently allocate a given work-unit to a suitable core for
execution. VOMP enables hardware/software collaboration with
online variability monitors in hardware and runtime scheduling
in software. The hardware provides online per-core characterization
of WUV metadata. This metadata is made available by
carefully placing key data structures in a shared L1 memory
and is used by VOMP schedulerss. Our results show that VOMP
greatly reduces the cost of timing error recovery compared to the
baseline schedulers of OpenMP, yielding speedup of 3%–36%
for tasks, and 26%–49% for sections. Further, VOMP reaches
energy saving of 2%–46% and 15%–50% for tasks, and sections,
respectively
Aging-aware compilation for GP-GPUs
No full textGeneral-purpose graphic processing units (GP-GPUs) offer high computational throughput using thousands of integrated processing elements (PEs). These PEs are stressed during workload execution, and negative bias temperature instability (NBTI) adversely affects their reliability by introducing new delay-induced faults. However, the effect of these delay variations is not uniformly spread across the PEs: some are affected more - hence less reliable - than others. This variation causes significant reductionin the lifetime of GP-GPU parts. In this article, we address the problem of "wear leveling" across processing units to mitigate lifetime uncertainty in GP-GPUs. We propose innovations in the static compiled code that can improve healing in PEs and stream cores (SCs) based on their degradation status. PE healing is a fine-grained very long instruction word (VLIW) slot assignment scheme that balances the stress of instructions across the PEs within an SC. SC healing is a coarse-grained workload allocation scheme that distributes workload across SCs in GP-GPUs. Both schemes share a common property: they adaptively shift workload from less reliable units to more reliable units, either spatially or temporally. These software schemes are based on online calibration with NBTI monitoring that equalizes the expected lifetime of PEs and SCs by regenerating adaptive compiled codes to respond to the specific health state of the GP-GPUs. We evaluate the effectiveness of the proposed schemes for various OpenCL kernels from the AMD APP SDK on Evergreen and Southern Island GPU architectures. The aging-aware healthy kernels generated by the PE (or SC) healing scheme reduce NBTI-induced voltage threshold shift by 30% (77% in the case of SCs), with no (moderate) performance penalty compared to the naive kernels
Task scheduling strategies to mitigate hardware variability in embedded shared memory clusters
Get PDFManufacturing and environmental variations cause timing errors that are typically avoided by conservative design guardbands or corrected by circuit level error detection and correction. These measures incur energy and performance penalties. This paper considers methods to reduce this cost by expanding the scope of variability mitigation through the software stack. In particular, we propose workload deployment methods that reduce the likelihood of timing errors in shared memory clusters of processor cores. This and other methods are incorporated in a runtime layer in the OpenMP framework that enables parsimonious countermeasures against timing errors induced by hardware variability. The runtime system 'introspectively' monitors the costs of tasks execution on various cores and transparently associates descrIPtive metadata with the tasks. By utilizing the characterized metadata, we propose several policies that enhance the cluster choices for scheduling tasks to cores according to measured hardware variability and system workload. We devise efficient task scheduling strategies for simultaneous management of variability and workload by exploiting centralized and distributed approaches to workload distribution. Both schedulers surpass current state-of-the-art approaches; the distributed (or the centralized) achieves on average 30% (or 17%) energy, and 17% (4%) performance improvement
On KKLT/CFT and LVS/CFT dualities
Get PDFWe present a general discussion of the properties of three dimensional CFT duals to the AdS string theory vacua coming from type IIB Calabi-Yau flux compactifi- cations. Both KKLT and Large Volume Scenario (LVS) minima are considered. In both cases we identify the large ‘central charge’, find a separation of scales between the radius of AdS and the size of the extra dimensions and show that the dual CFT has only a limited number of operators with small conformal dimension. Differences between the two sets of duals are identified. Besides a different amount of supersymmetry (N = 1 for KKLT and N = 0 for LVS) we find that the LVS CFT dual has only one scalar operator with O(1) conformal dimension, corresponding to the volume modulus, whereas in KKLT the whole set of h1,1 K ̈ahler moduli have this property. Also, the maximal number of degrees of freedom is estimated to be larger in LVS than in KKLT duals. In both cases we explic- itly compute the coefficient of the logarithmic contribution to the one-loop vacuum energy which should be invariant under duality and therefore provides a non-trivial prediction for the dual CFT. This coefficient takes a particularly simple form in the KKLT case
Pible: Battery-free mote for perpetual indoor BLE applications
No full textSmart building applications require a large-scale deployment of sensors distributed across the environment. Recent innovations in smart environments are driven by wireless networked sensors as they are easy to deploy. However, replacing these batteries at scale is a non-trivial, labor-intensive task. Energy harvesting has emerged as a potential solution to avoid battery replacement but requires compromises such as application specific design, simplified communication protocol or reduced quality of service. We explore the design space of battery-free sensor nodes using commercial off the shelf components, and present Pible: a Perpetual Indoor BLE sensor node that leverages ambient light and can support numerous smart building applications. We analyze node-lifetime, quality of service and light availability trade-offs and present a predictive algorithm that adapts to changing lighting conditions to maximize node lifetime and application quality of service. Using a 20 node, 15- day deployment in a real building under varying lighting conditions, we show feasible applications that can be implemented using Pible and the boundary conditions under which they can fail
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