209,309 research outputs found
Asymmetric gate induced drain leakage and body leakage in vertical MOSFETs with reduced parasitic capacitance
No full textVertical MOSFETs, unlike conventional planar MOSFETs, do not have identical structures at the source and drain, but have very different gate overlaps and geometric configurations. This paper investigates the effect of the asymmetric source and drain geometries of surround-gate vertical MOSFETs on the drain leakage currents in the OFF-state region of operation. Measurements of gate-induced drain leakage (GIDL) and body leakage are carried out as a function of temperature for transistors connected in the drain-on-top and drain-on-bottom configurations. Asymmetric leakage currents are seen when the source and drain terminals are interchanged, with the GIDL being higher in the drain-on-bottom configuration and the body leakage being higher in the drain-on-top configuration. Band-to-band tunneling is identified as the dominant leakage mechanism for both the GIDL and body leakage from electrical measurements at temperatures ranging from ?50 to 200?C. The asymmetric body leakage is explained by a difference in body doping concentration at the top and bottom drain–body junctions due to the use of a p-well ion implantation. The asymmetric GIDL is explained by the difference in gate oxide thickness on the vertical (110) pillar sidewalls and the horizontal (100) wafer surface
baby-groot-test-index-files
No full text<p>This repo is to host BABY-GROOT index files</p>
Humans and nature : public visions on their interrelationship
No full textContains fulltext :
81997.pdf (Publisher’s version ) (Open Access)Radboud Universiteit Nijmegen, 08 september 2010Promotor : Groot, W.T. de Co-promotor : Arts, B.J.M.168 p
High quality Schottky contacts for limiting leakage currents in Ge-based Schottky barrier MOSFETs
No full textSchottky barrier (SB) Ge channel MOSFETs suffer from high drain-body leakage at the required elevated substrate doping concentrations to suppress source-drain leakage. Here we show that electrodeposited Ni-Ge and NiGe/Ge Schottky diodes on highly doped Ge show low off current, which might make them suitable for SB p-MOSFETs. The Schottky diodes showed rectification of up to 5 orders in magnitude. At low forward biases the overlap of the forward current density curves for the as deposited Ni/n-Ge and NiGe/n-Ge Schottky diodes indicates Fermi-level pinning in the Ge band gap. The SB height for electrons remains virtually constant at 0.52 eV (indicating a hole barrier height of 0.14 eV) under various annealing temperatures. The series resistance decreases with increasing annealing temperature in agreement with four point probe measurements indicating the lower specific resistance of NiGe as compared to Ni, which is crucial for high drive current in SB p-MOSFETs. We show by numerical simulation that by incorporating such high quality Schottky diodes in the source/drain of a Ge channel PMOS, highly doped substrate could be used to minimize the subthreshold source to drain leakage current
Self-aligned silicidation of surround gate vertical MOSFETs for low cost RF applications
No full textWe report for the first time a CMOS-compatible silicidation technology for surround-gate vertical MOSFETs. The technology uses a double spacer comprising a polysilicon spacer for the surround gate and a nitride spacer for silicidation and is successfully integrated with a Fillet Local OXidation (FILOX) process, which thereby delivers low overlap capacitance and high drive-current vertical devices. Silicided 80-nm vertical n-channel devices fabricated using 0.5-?m lithography are compared with nonsilicided devices. A source–drain (S/D) activation anneal of 30 s at 1100 ?C is shown to deliver a channel length of 80 nm, and the silicidation gives a 60% improvement in drive current in comparison with nonsilicided devices. The silicided devices exhibit a subthreshold slope (S) of 87 mV/dec and a drain-induced barrier lowering (DIBL) of 80 mV/V, compared with 86 mV/dec and 60 mV/V for nonsilicided devices. S-parameter measurements on the 80-nm vertical nMOS devices give an fT of 20 GHz, which is approximately two times higher than expected for comparable lateral MOSFETs fabricated using the same 0.5-?m lithography. Issues associated with silicidation down the pillar sidewall are investigated by reducing the activation anneal time to bring the silicided region closer to the p-n junction at the top of the pillar. In this situation, nonlinear transistor turn-on is observed in drain-on-top operation and dramatically degraded drive current in source-on-top operation. This behavior is interpreted using mixed-mode simulations, which show that a Schottky contact is formed around the perimeter of the pillar when the silicided contact penetrates too close to the top S/D junction down the side of the pillar
Treatise on magnetocaloric MnFe(Si,P) compounds : a first-principles study
No full textContains fulltext :
160398.pdf (Publisher’s version ) (Open Access)RU Radboud Universiteit, 10 oktober 2016Promotor : Groot, R.A. de Co-promotor : Wijs, G.A. deIX, 113 p
P. Mag. J. V. De Groot, O. P., Levenswijding
No full textVan Cauwelaert F. P. Mag. J. V. De Groot, O. P., Levenswijding. In: Revue néo-scolastique. 10ᵉ année, n°39, 1903. p. 328
P. Mag. J. V. De Groot, O. P., Levenswijding
No full textVan Cauwelaert F. P. Mag. J. V. De Groot, O. P., Levenswijding. In: Revue néo-scolastique. 10ᵉ année, n°39, 1903. p. 328
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