1,040 research outputs found
A Distributed Architecture to Check Global Properties for Post-Silicon Debug
Get PDFPost-silicon validation and debug, or ensuring that software executes correctly on the silicon of a multi-processor system-on-chip (MPSOC) is complicated, as it involves checking global properties that are distributed on the chip. In this paper we define an architecture to non-intrusively observe global properties at run time using distributed monitors. The architecture enables to perform actions when a property holds, such as stopping (part of) the system for inspection. We apply this architecture to the problem of software races that result in incorrect communication between concurrent tasks on different processors. In a case study, where we implemented monitors, event distribution, and instruments to stop communication between intellectual property (IP) blocks, we demonstrate that these races can be detected and classified as timing violations or as FIFO protocol violations.©2010 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. Erik Larsson, Bart Vermeulen and Kees Goossens, A Distributed Architecture to Check Global Properties for Post-Silicon Debug, 2010, IEEE European Test Symposium (ETS'10), Prague, Czech Republic, May 24-28, 2010.</p
Customizing and hardwiring on-chip interconnects in FPGAs
Get PDFThis thesis presents our investigations on how to efficiently utilize on-chip wires to improve network performance in reconfigurable hardware. A fieldprogrammable gate array (FPGA), as a key component in a modern reconfigurable platform, accommodates many-millions of wires and the on-demand reconfigurability is realized using this abundance of wires. Modern FPGAs become computationally powerful as hardware IP (intellectual property) modules such as embedded memories, processor cores, and DSP modules are accommodated. However, the performance and the cost of the inter-IP communication remains a main challenge. We meet this challenge in two aspects. First, conventional general-purpose on-chip networks suffer from high area cost when they are mapped onto the reconfigurable fabric. To reduce the area cost, we present a topology customization technique for a given set of applications. Specifically, we present an application-specific crossbar switch, crossbar schedulers, point-to-point interconnects, and circuit-switched networks-on-chip (NoCs) that reside on top of a reconfigurable fabric. As a result, by establishing only the necessary network resources, our customized interconnects provide significantly reduced cost compared to general-purpose on-chip networks. Second, while the reconfigurability is a key benefit in FPGAs, it is traded off by decreased performance and increased cost. This is mainly because of the bit-level reconfigurable interconnects. To increase performance and reduce cost, we propose to replace the bit-level reconfigurable wires by hardwired circuit-switched interconnects for the inter-IP communication. Specifically, we present hardwired crossbars and a circuit-switched NoC interconnect fabric. We describe the advantages of the hardwired networks evidenced by the quantified performance analysis, network simulation, and an implementation. As a result, the hardwired networks provide two orders of magnitude better performance per area than the networks that are mapped onto the reconfigurable fabric.Computer EngineeringElectrical Engineering, Mathematics and Computer Scienc
Resource Allocation in Time-Division-Multiplexed Networks on Chip
Get PDFOne of the challenges of engineering is to make the best possible use of the available resources, or in other words allocating the resources in such a way as to maximize the overall profit. In the context of networks on chip the resources are represented by the communication bandwidth and the final profit is the performance of an application supported by the network on chip. In this thesis we focus on networks on chip providing guaranteed performance, i.e. guaranteeing for each application the delivery of a requested bandwidth. In these networks, hardware resources are allocated and assigned to each application for its entire lifetime. We discuss several solutions for delivering the allocated bandwidth, and we propose models which allow us to evaluate the performance of these solutions. Starting from a general, rate-based allocation model we gradually add more architectural restrictions that lower the implementation cost, but at the same time sacrifice some performance. NoCs with allocation based on discrete rates are very common and include priority-based, TDM, SDM, FDM, and other NoCs. They all partition the bandwidth available on the network links into discrete units. In the case of TDM NoCs these units are called time slots. The problem of resource allocation in TDM NoCs consists of finding paths through the network between the nodes that wish to communicate, and selecting along these paths a set of free time slots that is sufficiently large to fulfill the application requirements. After allocation the bandwidth is guaranteed. In this thesis, we propose, implement and evaluate allocation algorithms for all the proposed performance models. Particular effort is dedicated to allocation algorithms for the contention-free routing model, a restrictive, but low-cost form of TDM where allocation is particularly challenging. Our allocation algorithms deal both with spatial allocation, i.e., the selection of a specific path out of the available paths through the network, and temporal allocation, i.e., along the time axis. The latter is used for optimizing bandwidth usage and latency which we will both discuss in depth. We propose two algorithms for the allocation of slots in the time domain, both of which we show to be optimal. We also demonstrate how the TDM schedule can be computed at run time, with low computational requirements. We demonstrate a system performing run-time allocation in FPGA and we implement hardware acceleration for the more expensive operations used by the allocation algorithm. We propose a synthesizable NoC implementation based on the contention-free-routing model, called dAElite. Our proposal uses existing design flows but has better performance and reduced hardware cost. The network supports some of the less restrictive models that we have previously introduced thus allowing a better allocation of resources. Finally, we present how the communication requests of the IPs are handled by the interconnect. We propose optimizations such as write coalescing and latency hiding techniques at the interface between IPs and the NoC and we demonstrate the performance benefits of the proposed approach in real applications. The main conclusions of this thesis are that, compared to an ideal rate-based NoC offering guaranteed bandwidth, introducing fixed discrete allocation units causes a performance loss of 18% while using headers loses another 15%, under the considered, realistic scenarios. Other factors, such as topology, in-order delivery, etc. cause only a minor performance loss. We find AEthereal to lose 46% compared to an ideal rate-based network, while the dAElite network introduced here loses less than 26% and is at the same time less expensive to implement.Computer EngineeringElectrical Engineering, Mathematics and Computer Scienc
Field Programmable Gate Arrays with Hardwired Networks on Chip
Get PDFTechnology down-scaling and platform-based designs have enforced a number of application and architecture trends for system-on-chip (SOC) designs. A modern SOC is now a multi-functional machine that can execute a large number of complex applications by using tens or even hundreds of intellectual properties (IPs). Meanwhile, due to a number of constraints, e.g., short time to market, fickle market demands, and high non-recurring engineering (NRE) costs to name a few, Field Programmable Gate Arrays (FPGAs) have gained popularity to implement SOC designs. The applications in an SOC can be dynamically started and stopped thus forming multiple use-cases. The applications can also have diverse Quality-of-Service (QoS) constraints ranging from non real-time to soft, firm, and hard real-time constraints. At the same time the IP cores in an SOC are heterogenous in nature and run at diverse clock frequencies. The IPs can be microprocessors, DSP slices, memories, and ALU units, etc. The increasing number and diversity of applications and IPs require a powerful onchip communication architecture for quick integration and appropriate QoS. In contemporary FPGAs the onchip interconnect would be soft, i.e., programmed in the configurable fabric. The above-mentioned application and architecture trends have triggered a series of problems. (1) An increasing number of applications on an FPGA often requires dynamic reconfiguration of an application, which in turn can produce interference with other running applications. (2) The increasing complexity of an application may mean that it can not be mapped entirely on the FPGA, which in turn can encounter loss of state of data during intra-application dynamic partial reconfiguration. (3) The diverse natures of applications make it difficult to fulfill the Quality-of-Service constraints of an application. (4) Similarly, it is hard to achieve (physical) timing closure in an SOC, because of the increasing number and diversity of the IP cores. (5) The technology downscaling leads to FPGA architectures that are more prone to faults, e.g., configuration memories and logic elements in an FPGA can be stuck at a particular value. (6) Because communication architecture and IPs are both mapped as soft IPs in the same logic plane of the FPGA, their placement has many restrictions to allow for dynamic partial reconfiguration. In this thesis, we aim to address the above-mentioned problems by proposing the architecture and design flow of a new FPGA. As the main contribution of the thesis, we propose the FPGA architecture with a hardwired network on chip (HWNoC), and multiple test, configuration, and functional regions (TCFRs). We call it hardwired, because the NoC in an FPGA is built in silicon and not by using the reconfigurable elements. By having a HWNOC we can have a globally asynchronous locally synchronous (GALS) environment, which in turn ensures that data is not lost during inter-IP communication. The HWNOC separates the communication and computation in two disjoint planes, which alleviates restrictions on the placement of IPs. As the second contribution of the thesis, we show how we can use the HWNOC to transport unified test, configuration, and functional data to TCFRs, for testing, faster configuration, and interference-free communication during execution of applications. As the third contribution of the thesis, we demonstrate that how the proposed design flow ensures predictable application behavior by fulfilling the QoS constraints. We also present a 3-tier reconfiguration model that uses the HWNOC, which ensures contention-free communication at architecture level, to overcome the problems of interference and state-loss during inter-application and intra-application reconfiguration respectively. Another contribution of the thesis is that it proposes a non-intrusive test methodology that uses the HWNOC as a test access mechanism to test the presence of faults reliability of FPGA architecture. In other words, the proposed methodology makes sure that applications are always reconfigured and executed on a reliable region of an FPGA, and without effecting the other running applications.Microelectronics & Computer EngineeringElectrical Engineering, Mathematics and Computer Scienc
Multithreading for Embedded Reconfigurable Multicore Systems
No full textIn this dissertation, we address the problem of performance efficient multithreading execution on heterogeneous multicore embedded systems. By heterogeneous multicore embedded systems we refer to those, which have real-time requirements and consist of processor tiles with General Purpose Processor (GPP), local memory, and one or more coprocessors running on reconfigurable logic ((e)FPGA). We improve system performance by combining two common methods. The first method is to exploit the available application parallelism by means of multithreading program execution. The second method is to provide hardware acceleration for the most computationally intensive kernels. More specifically our scientific approach is as follows: we categorize the existing program execution models from the processor-coprocessor synchronization prospective and we introduce new parallel execution models. Then, we provide a high-level architectural abstraction of those execution models and programming paradigm that describes and utilizes them. Furthermore, we propose a microarchitectural support for the identified execution models. The functionality of the microarchitectural extensions is encapsulated in a new reconfigurable coprocessor, called Thread Interrupt State Controller (TISC). To improve the overall system performance, we employ the newly proposed program execution models to transfer highly time-variable and time-consuming Real-Time Operating System (RTOS) and application kernels from software, i.e., executed on the GPPs, to hardware, i.e., executed on the reconfigurable coprocessors. We refer to this reconfigurable coprocessor as Hardware Task Status Manager (HWTSM). Due to the properties of the newly introduced execution models such as parallel execution and constant response time, we preserve the predictability and composability at application level. Last but not least, we introduce a framework for distribution of slack information (idle processor time) among processor tiles. In the proposed framework we employ one of the newly introduced parallel processor-coprocessor execution models. We refer to the new reconfigurable coprocessor as RS. We use the extra slack information obtained through our framework for Dynamic Voltage Frequency Scaling that reduces the overall energy consumption. Based on the available experimental results with synthetic and real applications, we improve the system speedup up to 19.6 times with the help of the Thread Interrupt State Controller. Furthermore, we reduce RTOS cost with the help of the Hardware Task Status Manager, which results in additional application acceleration up to 13.3%. Last but not least, we improve the system energy consumption up to 56.7% over current state of the art with the help of inter-tile remote slack information distribution framework. Overall, with the help of our contributions, the system performance is improved, the predictability and composability are preserved, all with reduced energy consumption.Software and Computer TechnologyElectrical Engineering, Mathematics and Computer Scienc
High-Level Power Estimation and Optimization of DRAMs
No full textEmbedded systems have become an integral part of our life in the last few years in multifarious ways, be it in mobile phones, portable audio players, smart watches or even cars. Most embedded systems fall under the category of consumer electronics, such as televisions, mobile devices, and wearable electronics. With several players competing in this market, manufacturers of embedded systems continue to add more functionality to these devices to make them more user-friendly, and often equip them with a very high resolution display and graphics support, and better computing and Internet capabilities. Unfortunately, they are often constrained by tight power/energy budgets, since battery capacity does not improve at the same rate as computing power. While there is clearly much progress to be made in harnessing all the possibilities of embedded systems, limitations in battery capacities, thermal constraints and power/energy budgets surely hinder this progress. Although technology scaling has traditionally addressed both the power minimization and high-performance requirements, with Moore's law nearing its limits, the development of energy-efficient system designs has become critically important. Thus, to be able to continue to provide new and improved features in embedded systems, design-time and run-time power management and minimization holds the key. As a consequence, power optimization has become one of the most defining aspects of designing modern embedded systems. To design such high-performance and energy-efficient embedded systems, it is extremely important to address two basic issues: (1) accurate estimation of power consumption of all system components during early design stages and (2) deriving power optimization solutions that do not negatively impact system performance. In this thesis, we aim to address these two issues for one of the most important components in modern embedded systems: DRAM memories. Towards this, we propose a high-precision DRAM power model (DRAMPower) and a set of performance-neutral DRAM power-down strategies. DRAMPower is a high-level DRAM power model that performs high-precision modeling of the power consumption of different DRAM operations, state transitions and power-saving modes at the cycle-accurate level. To further improve the accuracy of DRAMPower's power/energy estimates, we derive better than worst-case and realistic measures for the JEDEC current metrics instead of vendor provided worst-case measures from device datasheets. Towards this, we modify a SPICE-based circuit-level DRAM architecture and power model and derive better than worst-case current measures under nominal operating conditions applicable to a majority of DRAM devices (>97%) with any given configuration (capacity, data width and frequency). Besides these better than worst-case current measures, we also propose a generic post-manufacturing power and performance characterization methodology for DRAMs that can help identify the realistic current estimates and optimized set of timing measures for a given DRAM device, thereby further improving the accuracy of the power and energy estimates for that particular DRAM device. To optimize DRAM power consumption, we propose a set of performance-neutral DRAM power-down strategies coupled with a power management policy that for any given use-case (access granularity, page policy and memory type) achieves significant power savings without impacting its worst-case performance (bandwidth and latency) guarantees. We verify the pessimism in DRAM currents and four critical DRAM timing parameters as provided in the datasheets, by experimentally evaluating 48 DDR3 devices of the same configuration. We further derive optimal set of timings using the performance characterization algorithm, at which the DRAM can operate successfully under worst-case run-time conditions, without increasing its energy consumption. We observed up to of 33.3% and 25.9% reduction in DRAM read and write latencies and 17.7% and 15.4% improvement in energy efficiency. We validate DRAMPower model against a circuit-level DRAM power model and verify it against real power measurements from hardware for different DRAM operations. We observed between 1-8% difference in power estimates, with an average of 97% accuracy. We also evaluated the power-management policy and power-down strategies and observed significant energy savings (close to theoretical optimal) at very marginal average-case performance penalty without impacting any of the original latency and bandwidth guarantees.Microelectronics & Computer EngineeringElectrical Engineering, Mathematics and Computer Scienc
Composable Virtual Platforms for Mixed-Criticality Embedded Systems
No full textRecent trends show a steady increase towards concurrently executing more and more applications on a single embedded system. Multi-Processor System-on-Chip (MPSoC) architectures are proposed to allow complex design of embedded systems. This is achieved by integrating as many processing resources as possible on a single chip and therefore enabling the execution of multiple applications on a single embedded System-on-Chip (SoC). Due to cost implications, the applications have to share some resources when executing concurrently on these systems. To fully exploit the computational power of an MPSoC, an application is further split into a number of concurrent tasks. Depending on the intrinsic behavior of an application, its tasks may be either data- or time-interdependent, and accordingly, two different models of computation, namely data-driven and time-driven, are used to implement such an application. Besides this, applications typically have timing requirements expressed in three categories of firm, soft, and non real-time requirements. In a mixed time-criticality system, the applications that execute concurrently on a single embedded platform have widely varying real-time requirements, where resource sharing causes interference between the applications. In order to execute real-time applications on an embedded platform, the system has to be predictable to ensure that the timing requirements of the applications are met. Moreover, to enable independent design, verification, and integration of mixed-criticality applications, the system has to be strongly composable, i.e., concurrently executing applications are temporally isolated in such a way that the actual-case temporal behavior of each application is unaffected at the cycle-level. In this way, temporal interference between the applications is completely prevented. In this dissertation, we address two main challenges in designing and prototyping mixed time-criticality systems: (i) realizing strongly composable Virtual Platforms (VPs) for mixed-criticality embedded systems, and (ii) proposing a uniform abstract execution layer for applications expressed with different models of computation. Here, we target time-driven models of computation and, Kahn Process Network (KPN) and dataflow (specifically, Cyclo-Static DataFlow (CSDF)) as the two variants of data-driven models of computation. On the basis of these challenges we answer the main research question of how to design and execute multiple applications concurrently on an embedded system, given that the applications are realized with different models of computation and having different levels of time-criticality? This dissertation proposes a solution to create a VP for every application by virtualizing all the hardware resources that are involved in the execution of the applications. For this, a temporal partitioning technique is applied to the CompSOC hardware architecture. On top of this architecture, the CoMik microkernel is designed as a minimum privileged software layer to provide resource partitioning. CoMik creates, controls and schedules processor partitions, and executes an application in its partition by virtualizing the processor’s software hooks, offering an Application Programming Interface (API) to each application to use its allocated resources. Applications can therefore execute directly on their virtual platforms in the same manner as on a dedicated hardware platform. However there exists an execution abstraction gap between the models of computation’s semantics and the platform’s primitive operations. To fill this gap, a model of execution is proposed to define a common set of execution operations and their orchestrations in order to implement an specific model of computation. The model of execution is implemented in the form of a lightweight operating system library, namely CompOSe, which is instantiated in every partition of a VP. CompOSe is designed in a number of software units and is implemented in such a way that it does not introduce any unpredictability in executing an application and complies with the composability property of the system provided by the CoMik microkernel. We demonstrate that our proposed technique enables concurrent composable, predictable execution of applications realized with multiple models of computation by using two experimentation setups. One, a Matlab simulation environment is used to investigate the temporal behavior of the CoMik microkernel. Two, an FPGA prototype of the CompSOC platform is used to study the composability property and support of multiple models of computation by the CompOSe Real-Time Operating System.Computer Science & EngineeringElectrical Engineering, Mathematics and Computer Scienc
Improving the scalability of multicore systems with a focus on H.264 video decoding
No full textIn pursuit of ever increasing performance, more and more processor architectures have become multicore processors. As clock frequency was no longer increasing rapidly and ILP techniques showed diminishing results, increasing the number of cores per chip was the natural choice. The transistor budget is still increasing and thus it is expected that within ten years chips can contain hundreds of high performance cores. Scaling the number of cores, however, does not necessarily translate into an equal scaling of performance. In this thesis, we propose several techniques to improve the performance scalability of multicore systems. With those techniques we address several key challenges of the multicore area. First, we investigate the effect of the power wall on future multicore architecture. Our model includes predictions of technology improvements, analysis of symmetric and asymmetric multicores, as well as the influence of Amdahl's Law. Second, we investigate the parallelization of the H.264 video decoding application, thereby addressing application scalability. Existing parallelization strategies are discussed and a novel strategy is proposed. Analysis shows that using the new parallelization strategy the amount of available parallelism is in the order of thousands. Several implementations of the strategy are discussed, which show the difficulty and the possibility of actually exploiting the available parallelism. Third, we propose an Application Specific Instruction Set (ASIP) processor for H.264 decoding, based on the Cell SPE. ASIPs are energy efficient and allow performance scaling in systems that are limited by the power budget. Finally, we propose hardware support for task management, of which the benefits are two-fold. First, it supports the SARC programming model, which is a task-based dataflow programming model based on StarSS. By providing hardware support for the most time-consuming part of the runtime system, it improves the scalability. Second, it reduces the parallelization overhead, such as synchronization, by providing fast hardware primitives.Computer EngineeringElectrical Engineering, Mathematics and Computer Scienc
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