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Methodologies and Toolflows for the Predictable Design of Reliable and Low-Power NoCs
No full textThere is today the unmistakable need to evolve design methodologies and
tool
ows for Network-on-Chip based embedded systems. In particular, the
quest for low-power requirements is nowadays a more-than-ever urgent dilemma.
Modern circuits feature billion of transistors, and neither power management
techniques nor batteries capacity are able to endure the increasingly higher
integration capability of digital devices. Besides, power concerns come together
with modern nanoscale silicon technology design issues.
On one hand, system failure rates are expected to increase exponentially at
every technology node when integrated circuit wear-out failure mechanisms
are not compensated for. However, error detection and/or correction mechanisms
have a non-negligible impact on the network power.
On the other hand, to meet the stringent time-to-market deadlines, the design
cycle of such a distributed and heterogeneous architecture must not be
prolonged by unnecessary design iterations.
Overall, there is a clear need to better discriminate reliability strategies and
interconnect topology solutions upfront, by ranking designs based on power
metric. In this thesis, we tackle this challenge by proposing power-aware
design technologies.
Finally, we take into account the most aggressive and disruptive methodology
for embedded systems with ultra-low power constraints, by migrating
NoC basic building blocks to asynchronous (or clockless) design style. We
deal with this challenge delivering a standard cell design methodology and
mainstream CAD tool
ows, in this way partially relaxing the requirement
of using asynchronous blocks only as hard macros
A Transition-Signaling Bundled Data NoC Switch Architecture for Cost-effective GALS Multicore Systems
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Asynchronous networks-on-chip (NoCs) are an appealing solution to tackle the synchronization challenge in modern multicore systems through the implementation of a GALS paradigm. However, they have found only limited applicability so far due to two main reasons: the lack of proper design tool flows as well as their significant area footprint over their synchronous counterparts. This paper proposes a largely unexplored design point for asynchronous NoCs, relying on transition-signaling bundled data, which contributes to break the above barriers. Compared to an existing lightweight synchronous switch architecture, xpipesLite, the post-layout asynchronous switch achieved a 71% reduction in area, up to 85% reduction in overall power consumption, and a 44% average reduction in energy-per-flit, while mastering the more stringent timing assumptions of this solution with a semi-automated synthesis flow
debug noc architecture with accurate timestamping for GALS SoCs
No full textThis work proposes a flexible and modular solution for nonintrusive tracing and debugging of software on embedded SoC platforms. It utilizes a separate, dedicated Network-on-Chip (NoC) interconnect with a hierarchical unidirectional ring topology to connect a multitude of monitoring devices. The devices are controlled via a debugger attached to the NoC. They use the network to receive control information and send back observations, which the debugger uses to construct a trace. The system utilizes a very accurate and efficient differential timestamping approach. It allows working with multi-synchronous SoCs, identifying concurrencies and other temporal properties in the SoC and coping with partial power downs and clock gatings. The proposed solution requires a low amount of hardware resources and at the same time provides unmatched capabilities
System-level infrastructure for boot-time testing and configuration of networks-on-chip with programmable routing logic
No full textNetworks-on-chip need to survive to manufacturing faults in
order to sustain yield. An effective testing and configuration strategy
however implies two opposite requirements. On one hand,
a fast and scalable built-in self-testing and self-diagnosis procedure
has to be carried out concurrently at NoC switches. On
the other hand, programming the NoC routing mechanism to go
around faulty links and switches can be optimally performed by
a centralized controller with global network visibility. This paper
proposes a global hardware infrastructure that meets such requirements
by means of a fault-tolerant dual network architecture and a
configuration strategy for reprogramming the routing mechanism
of each switch. This is the first complete infrastructure for testing
and reconfiguring a NoC based on reprogrammable routing logic
Power efficiency of switch architecture extensions for fault tolerant NoC design
No full textThe increasingly parallel landscape of embedded computing platforms is bringing the reliability concern for the on-chip interconnection network (NoC) to the forefront. While very few works in the open literature bring their error recovery mechanisms down to microarchitectural and physical implementation, this paper documents the effort of optimizing a baseline NoC switch architecture for different fault-tolerant strategies against single-event upsets. As key contributions achieved, we not only come up with a new efficient fault-tolerant flow control protocol, but also we contrast correction vs. retransmission oriented switch microarchitectures, each implementing both data and control path protection, with physical implementation awareness. The accuracy of the analysis methodology enables us to report counterintuitive power-reliability trade-offs between the design points, serving as guidelines for implementing fault-tolerant communication in a power-constrained environment
A vertically integrated and interoperable multi-vendor synthesis flow for predictable noc design in nanoscale technologies
No full textWe deliver a design flow for the synthesis and convergence of application-specific networks-on-chip. The flow comes with novel features that can better address nanoscale design challenges: front-end driven floorplanning, dynamic IR-drop minimization, fast and accurate system-level power grid modeling, predictable link design. Above all, such features are addressed by different prototype engines, even from different vendors, that can be smoothly integrated into the flow by means of a common specification format called Communication Exchange Format (CEF), that enables unprecedented tool interactions. This flow is validated by means of an extensive demonstration framework
Crossbar replication vs. sharing for virtual channel flow control in asynchronous NoCs: A comparative study
No full textIn on-chip interconnection networks, performance optimization techniques can be often achieved in two opposite ways: by making control logic more complex inside switches, or by pushing design complexity to the switch boundaries. The implementation of virtual channel (VC) flow control is an important application domain of this design trade-off. The data path of VC switches typically exhibits replicated buffers. The underlying philosophy (i.e., resource replication) can be pushed to the limit, thus incuring an apparently high area cost, while simplifying the switch control path. On the other hand, unreplicated resources require complex control logic for the sake of their efficient sharing among virtual networks. Investigating this design tradeoff is especially important for asynchronous networks, where the synthesis of complex control circuits is a challenge. This paper is a first step toward a design space exploration of VC implementation techniques for transition-signalling bundled-dat...In on-chip interconnection networks, performance optimization techniques can be often achieved in two opposite ways: by making control logic more complex inside switches, or by pushing design complexity to the switch boundaries. The implementation of virtual channel (VC) flow control is an important application domain of this design trade-off. The data path of VC switches typically exhibits replicated buffers. The underlying philosophy (i.e., resource replication) can be pushed to the limit, thus incuring an apparently high area cost, while simplifying the switch control path. On the other hand, unreplicated resources require complex control logic for the sake of their efficient sharing among virtual networks. Investigating this design tradeoff is especially important for asynchronous networks, where the synthesis of complex control circuits is a challenge. This paper is a first step toward a design space exploration of VC implementation techniques for transition-signalling bundled-data asynchronous NoCs, and contrasts a VC switch with replicated crossbars against a unified-crossbar architecture relying on multistage switch allocation
Going Beyond Counting First Authors in Author Co-citation Analysis
Full text linkThe present study examines one of the fundamental aspects of author co-citation analysis (ACA) - the way co-citation
counts are defined. Co-citation counting provides the data on which all subsequent statistical analyses and mappings
are based, and we compare ACA results based on two different types of co-citation counting - the traditional type that
only counts the first one among a cited work's authors on the one hand and a non-traditional type that takes into
account the first 5 authors of a cited work on the other hand. Results indicate that the picture produced through this non-traditional author co-citation counting contains more coherent author groups and is therefore considerably clearer. However, this picture represents fewer specialties in the research field being studied than that produced through the traditional first-author co-citation counting when the same number of top-ranked authors is selected and analyzed. Reasons for these effects are discussed
Variations on the Author
Full text link“Variations on the Author” discusses two of Eduardo Coutinho’s recent films (Um Dia na Vida, from 2010, and Últimas Conversas, posthumously released in 2015) and their contribution to the general question of documentary authorship. The director’s filmography is characterized by a consistent yet self-effacing form of authorial self-inscription: Coutinho often features as an interviewer that rather than express opinions propels discourses; an interviewer that is good at listening. This mode of self-inscription characterizes him as an author who is not expressive but who is nonetheless markedly present on the screen. In Um Dia na Vida, however, Coutinho is completely absent form the image, while Últimas Conversas, on the contrary, includes a confessional prologue that moves the director from the margins to the center of his films. This article examines the ways in which these works stand out in the filmography of a director who offers new insights into the notion of cinematic authorship
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