1,720,952 research outputs found
Aging Mitigation Schemes for Embedded Memories
No full textWith the continuous miniaturization of CMOS technology into the nanometer regime, the reliability of SRAM memories is threatened by accelerated transistor aging such as Bias Temperature Instability (BTI), Hot Carrier Injection (HCI) and gate oxide breakdown. Among these mechanisms BTI is known to be the primary aging mechanism in nanoscale devices. The overall effect of BTI is a gradual increase of threshold voltage (Vth). BTI significantly reduces the Static Noise Margin (SNM) of an SRAM cell and makes it more susceptible to failures. To address the impact of BTI in memory array a variety of bit flipping techniques has been proposed. However, all the proposed bit flipping techniques require at least an additional column to store the inversion flag which imposes considerably large area overhead. In this thesis, we propose two techniques to mitigate BTI induced aging in embedded memory: aging-aware instruction encoding and self-controlled bit flipping; both schemes take the workload into consideration. The aging-aware instruction encoding technique is based on changing the encoding of the Instruction Set Architecture (ISA) in order to balance the occurrence probabilities of 1s and 0s and therefore minimize the impact of BTI in the embedded memory. To evaluate this scheme, we used the Leon2 processor for course case study. A C++ based simulation environment was used to exhaustively search for an encoding resulting in a balanced occurrence probabilities of 0s and 1s. The simulation results revels that on average up to 30% SNM degradation improvement. Self-controlled bit flipping is based on inverting the content of the memory array during write operation with respect to a specific bit of the written word referred to as flip bit; this bit is left untouched during the write and used as a reference bit to indicate either the written data is inverted or not. Simulation results show that up to 33% SNM degradation improvement can be achieved. The area overhead of the proposed technique is the flip circuitry only. For this reason, our technique saves 64% of the area overhead induced by the periodic flipping techniques.Computer EngineeringMicroelectronics & Computer EngineeringElectrical Engineering, Mathematics and Computer Scienc
The implementation of an MBAN gateway
No full textEpilepsy is a severe neurological disorder that affects every aspect of a patient’s life. Unfortunately, there is no complete cure for everyone on the market yet. However, a lot of work has been done on seizure prevention. The entire project details the proof of concept implementation of a secure and reliable MBAN (Medical Body Area Network) used for seizure prevention. The principal objective of the MBAN system is to set up and maintain secure connections between the nodes of the MBAN system and store and analyze the received data in the cloud. Therefore, a suitable gateway is needed, which is created in this work. The gateway concerns a mobile application constructed with the Flutter SDK. The main ability of the applicaton is to communicate with the implantable medical device, which in the demonstration is the node the gateway is connected to using BLE. The application is designed for Android and iOS and is connected to the AWS cloud service in which the data is stored and analyzed with a simple function that checks whether the received heart rate is above a certain threshold. This function can be easily replaced by a more extensive function. In addition, the application displays user health metrics such as the heart rate, connection state, and it can update the firmware of the implantable medical device. The security measures taken in this project concern setting up the BLE connection with an OOB (Out Of Band) channel for key sharing, after which the key is used to encrypt the data streams. Additionally, the data in the cloud is encrypted
RRAM Crossbar-Based Fault-Tolerant Binary Neural Networks (BNNs)
No full textComputation-In Memory (CIM) using RRAM crossbar array is a promising solution to realize energy-efficient neuromorphic hardware, such as Binary Neural Networks (BNNs). However, RRAM faults restrict the applicability of CIM for BNN implementation. To address this issue, we propose a fault tolerance framework to mitigate the impact of RRAM faults on the accuracy of CIM-based BNN hardware. Evaluation results using MNIST, Fashion-MNIST and CIFAR-10 datasets demonstrate that the proposed framework outperforms the related works as it restores more than 99% of the RRAM fault induced accuracy reduction with relatively less overhead.Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.Computer EngineeringQuantum & Computer Engineerin
Benchmarking and Algorithm Optimization for SENeCA: A RISC-V-based Neuromorphic Processor
No full textWith recent breakthroughs in AI (Artificial Intelligence) technology, the impact of AI on society can be felt in various fields. The market for AI software, for example, reached a valuation of \$62 billion in 2022. A growing number of new computer architectures specialized in running these AI software were also developed. At first they were run on conventional CPUs (Central Processing Unit) and GPUs (Graphical Processing Units), but then more specialized hardware emerged, such as the TPU (Tensor Processing Unit). However, since algorithms in these AI software are generally data-intensive, the power consumption became a problem. Therefore, as many of these algorithms were based on biological neural networks, there is a growing interest to develop hardware similarly based on principles found these networks as well to replicate their efficiency. This new architecture is known as neuromorphic architecture. However, a new architecture does not come without challenges. As a nascent and fragmented field, neuromorphic computing in general lacks a standardized benchmarking suite or methodology. In other, more mature fields, benchmarks are a standard way of evaluating the performance of different designs objectively and fairly. This thesis aims to propose and demonstrate a benchmarking methodology and implementation flow for neuromorphic processors. This methodology aims to measure the important performance metrics for a neuromorphic processor, both on the small scale of individual synaptic operations, and the large scale of performing an actual workload. The chosen workload is a keyword spotting program based on a simple DNN architecture, which detects a specific phrase in an audio recording. This workload was chosen due to its potential application in an environment where energy is limited, such as an embedded device.The neuromorphic processor that is the target of this benchmarking is SENeCA (short for Scalable Energy-efficient Neuromorphic Computer Architecture), a flexible and scalable design developed at IMEC The Netherlands. To implement the keyword spotting program on SENeCA, the keyword spotting program was rewritten and parsed. Since no physical chip implementation of SENeCA exists at the time of writing, the program was run on SENeCA using a HDL simulator. The execution time of the program is measured in detail, taking into account not only the total time, but also the time required to complete the specific stages of program. Afterwards, the power consumption of SENeCA during the execution of the program was measured using a power estimation software, both for the entire chip and its individual components. This is done both in average mode, obtaining the average power consumption over the total execution time, and in time-based mode, providing insight to the peak power and fluctuations over time. Then, the energy to solution is calculated using the execution time and power consumption. This process is done in multiple iterations, with a specific optimization done each iteration using SENeCA's accelerators. This provides insight into the impact of each optimization to power consumption and performance. Finally, a measurement of the energy consumption of SENeCA per individual synaptic operations is also done, allowing estimates of the energy consumption of future implementations.Electrical Engineering | Embedded System
Memristor-Based Encryption For Free-Floating Neural Implants
No full textThe recent advances in the semiconductor industry have given rise to the development of highly scalable, wireless and battery-free neural-implant interfaces that enable brain monitoring and brain stimulation with high spatial and temporal resolution. Such implants are referred to as Free-Floating Neural Implants (FFNI), as the small size and untethered communication allow them to be scattered throughout the cortex. Nevertheless, the plethora of proposed interfaces have failed to mention and act against the potential security implications that may arise in highly-constrained FFNIs even though the U.S. Food and Drug Administration (FDA) has recently acknowledged the possibility of short-/long-range attacks on wireless Implantable Medical Devices (IMD). Hence, in this project, the existing threats in FFNIs are revealed, followed by the proposal of a memristor-based lightweight security approach to secure intracranial electromagnetic transmissions whilst considering the anticipated physical limitations of these constrained topologies. More specifically, a consolidated envisioned system is highlighted for which a read-only GIFT cipher is implemented. This lightweight encryption block primarily consists of a One-Transistor-One-Memristor (1T1R) crossbar structure for carrying out operations such as Substitution, Permutation, and addRoundKey, without destroying the resistive states and by only performing ‘read’ operations to maintain low power operation. With a footprint of 0.0034 mm2 the 1T1R-GIFT cipher reaches an average power and energy consumption of only 60.38 µW and 241.52 pJ, respectively. However, the performance does not exceed a CMOS-based implementation yet, whose footprint is similar but has roughly half the average power and energy consumption. This can be attributed mainly to the immaturity of the memristor technology. This work demonstrates that only after further advancements in memristor logic gates, crossbar topologies and fabrication processes, highly-constrained FFNIs can fully benefit from the scalable memristor-based security paradigm.Electrical Engineering | Embedded System
Going Beyond Counting First Authors in Author Co-citation Analysis
Full text linkThe present study examines one of the fundamental aspects of author co-citation analysis (ACA) - the way co-citation
counts are defined. Co-citation counting provides the data on which all subsequent statistical analyses and mappings
are based, and we compare ACA results based on two different types of co-citation counting - the traditional type that
only counts the first one among a cited work's authors on the one hand and a non-traditional type that takes into
account the first 5 authors of a cited work on the other hand. Results indicate that the picture produced through this non-traditional author co-citation counting contains more coherent author groups and is therefore considerably clearer. However, this picture represents fewer specialties in the research field being studied than that produced through the traditional first-author co-citation counting when the same number of top-ranked authors is selected and analyzed. Reasons for these effects are discussed
Dealing with Non-Idealities in Memristor Based Computation-In-Memory Designs
No full textComputation-In-Memory (CIM) using memristor devices provides an energy-efficient hardware implementation of arithmetic and logic operations for numerous applications, such as neuromorphic computing and database query. However, memristor-based CIM suffers from various non-idealities such as conductance drift, read disturb, wire parasitics, endurance and device degradation. These negatively impact the computation accuracy of CIM. It is therefore essential to deal with these non-idealities and fabrication imperfections in order to harness the full potential of CIM. This paper discusses the non-ideality challenges and provides potential solutions. Furthermore, the paper outlines the potential future directions for CIM architectures.Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.Computer EngineeringQuantum & Computer Engineerin
RRAM-based Low-Power Neuromorphic Computing Engine for Space Applications
No full textWith recent breakthroughs in AI and deep learning, applying these techniques to on-board computers for space applications has grown in interest to engineers on space applications. The space field brings its own challenges, such as reliability and power restrictions. The proposed solution in this work concerns a neuromorphic accelerator for a spiking neural network (SNN) designed using memristive devices (RRAM), dubbed the Newtype Learning Computer. To this end, this work presents the following contributions: A design for a behavioral VHDL implementation of a target SNN boasting software-level accuracy, specifically built for edge AI in space. We also present a characterized ASIC design of one layer of this SNN, analyzed using RTL design tools. An analysis of this same layer designed using Memristive Crossbar Arrays is also provided, and we present a comparison of both. When simulating 4096 neurons, the RRAM-based design shows 174x smaller area, power dissipation reduction of 27x energy reduction by 4 orders of magnitude and over 80x faster by latency compared to the CMOS-based design. This thesis presents a confident first step towards the use of RRAM-based neuromorphic accelerators for spiking neural networks in space-based applications.https://github.com/HeatPhoenix/NLC4Space Github repository for the project's files.Computer EngineeringElectrical Engineering | Embedded System
Mapping-aware Biased Training for Accurate Memristor-based Neural Networks
No full textMemristor-based computation-in-memory (CIM) can achieve high energy efficiency by processing the data within the memory, which makes it well-suited for applications like neural networks. However, memristors suffer from conductance variation problem where their programmed conductance values deviate from the desired values. Such variations lead to computational errors that result in degraded inference accuracy in CIM-based neural networks. In this paper, we present a mapping-aware biased training methodology to mitigate the impact of conductance variation on CIM-based neural networks. We first determine which conductance states of the memristor are inherently more immune to variation. The neural network is then trained under the constraint that important weights can only take numeric values which directly get mapped to such favorable states. Simulation results show that our proposed mapping-aware biased training achieves up to 2.4× hardware accuracy compared to the conventional training.Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.Computer EngineeringQuantum & Computer Engineerin
- …
