188 research outputs found
{4,4′-Dichloro-2,2′-[2,2-dimethylpropane-1,3-diylbis(nitrilomethanylylidene)]diphenolato}copper(II)
In the title Schiff base complex, [Cu(C19H18Cl2N2O2)], the CuII ion is coordinated in a distorted square-planar environment by two N atoms and two O atoms of the tetradentate ligand. The dihedral angle between the benzene rings is 36.86 (14)°. In the crystal, molecules are linked into inversion dimers by pairs of weak C—H...O hydrogen bonds. In addition, π–π [centroid–centroid distance = 3.7279 (16) Å] and weak C—H...π interactions are observed
{4,4′-Dimethoxy-2,2′-[2,2-dimethylpropane-1,3-diylbis(nitrilomethanylylidene)]diphenolato}copper(II) monohydrate
The asymmetric unit of the title compound, [Cu(C21H24N2O4)]·H2O, comprises half of a Schiff base complex and a water molecule. The CuII atom, water molecule and one C atom of the central propylene segment are located on a twofold rotation axis. The geometry around the CuII atom is distorted square-planar, supported by the N2O2 donor atoms of the coordinating ligand. The dihedral angle between the symmetry-related benzene rings is 42.56 (19)°. In the crystal, O—H...O hydrogen bonds involving the water molecule make an R21(6) ring motif. Complex molecules are linked into a chain along the c axis via C—H...O interactions
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Efficient Privacy-Preserving NN Inference at the Edge
Neural networks (NNs) have been widely adopted in practice to create predictive models in applications such as healthcare, financial services, and policy-making. As their use continues to grow, so does the risk of attacks against users' data and NNs. While traditionally, deep learning was constrained by computational power and off-chip memory bandwidth, such attacks impose new priorities in connection with security and privacy. Privacy-preserving deep learning addresses these issues by leveraging cryptographic primitives, e.g., homomorphic encryption and secure multiparty computation (MPC). MPC-based solutions offer a higher degree of flexibility by allowing different parties to train an NN model on their private data without revealing any information beyond the output. In this regard, combining MPC and deep learning enables a variety of privacy-preserving online services. As an example, to classify a picture, a customer can use an online deep learning service, where the service provider and the user engage in an MPC protocol instead of just uploading the picture. In doing so, the user obtains the classification result without revealing the input, while the provider can keep its model secret. Existing work in the area of MPC falls into two main classes: (1) MPC over Boolean circuits and (2) MPC over arithmetic circuits. While the former class relies on Yao’s garbled circuits and achieves constant communication complexity, secret-sharing (SS)-based solutions have been adopted to evaluate arithmetic circuits with a communication complexity linear in the multiplicative depth of the circuit. Nevertheless, there are MPC frameworks enjoying the benefits of both classes by combining them. Further optimization can be performed, which is applied in the context of private NN inference. Resource optimization is even more vital for applications where NNs run on resource-constrained edge devices. It has been shown in the literature that running MPC-based privacy-preserving NNs on FPGAs brings down the protocol execution time and power consumption within the practical limit. In line with such efforts, our work presents optimization techniques that utilize the full capability of the underlying FPGA hardware. More concretely, FPGAs' parallel processing and pipelining capabilities allow for faster computations essential in NN tasks. This is complemented by optimized memory access, which minimizes latency and maximizes data throughput. Moreover, the flexibility to develop custom instruction sets tailored for NN operations enhances protocol execution efficiency. Finally, the algorithm-hardware co-design approach ensures that both the NN algorithms and FPGA architecture are optimally aligned for performance, making FPGAs a powerful and efficient choice for the secure implementation of neural network accelerators through multi-party computation. Our results demonstrate that our approach uses significantly fewer hardware resources, up to 62.5 times fewer logical resources, and 66 times less memory than cutting-edge privacy-preserving NN interfaces. Furthermore, in scenarios where execution time is critical, our approach proves to be 2.5 times faster than the average execution time of the privacy-preserving NN inferences while closely matching the performance of the fastest state-of-the-art approaches to privacy-preserving NN inferences
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Large-Scale Characterization and Optimization of Bistable Rings
True random number generators (TRNGs) ideally produce unbiased, uncorrelated, and incompressible bits of information by extracting randomness from a stochastic process. These circuits help in secure communication, user authentication, and user identification protocols. Some TRNGs employ a bistable ring (BR), a digital logic circuit made up of an even number of inverters connected in a loop, as their core. When powered on, the BR oscillates and may settle into one of two states. We introduce concepts from nonlinear dynamic system analysis to determine whether the BR’s trajectories are random enough to be considered a promising entropy source in TRNGs. Our example BR simulations and Monte Carlo process variation experiments in Ngspice show that the BR’s trajectories are chaotic in the best-case scenario. We also study the FPGA realizations of BRs and observe periodic behavior in those implementations. Following these observations, we evolved instances of BRs using a genetic algorithm (GA) to determine whether one could surpass the chaotic and periodic characteristics of simulated and implemented BRs. According to our results for optimizing the BR trajectories’ complexity (measured by permutation entropy), some instances created by the GA could exhibit stochastic behavior
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Pre-Silicon Hierarchical Root-Cause Analysis of Side-Channel and Fault Vulnerabilities in System-on-Chip Designs
The growing complexity of modern System-on-Chip (SoC) designs has made analyzing security vulnerabilities, such as side-channel leakage and fault effects, increasingly challenging. Traditionally, vulnerability assessment is performed only after design fabrication. This post-silicon black-box approach provides limited insight into design details, identifying weaknesses without explaining their root causes and resulting in both challenging countermeasure design and costly refabrication. This dissertation argues that vulnerability assessment can be supported to an earlier (pre-silicon) stage, where full access to the internal design enables root-cause analysis and allows the development of more effective mitigations. The key lies in the hierarchical evaluation of vulnerabilities, which bridges software and hardware layers to capture how weaknesses propagate through the design hierarchy. We propose two primary contributions. First, sidechannel leakage can be addressed through a top-down analysis that traces how sensitive, software-defined asset (e.g., cryptographic key or nonce) influence lower hardware layers, enabling early detection and mitigation of leakage sources. Second, fault effects can be examined through a bottom-up analysis that tracks how hardware disturbances propagate to software outputs, revealing critical fault paths and guiding the design of effective mitigation
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Software-Induced Fault Attacks on Post-Quantum Signature Schemes
A digital signature is a digital equivalent of a handwritten signature or stamp which is used to validate the authenticity and integrity in digital communications like an email, a credit card transaction or a digital document. Digital signatures are mathematical schemes whose security is based on conjectured hard problems like discrete log or RSA moduli factorization. Unfortunately, these public-key cryptosystems are not quantum secure and large scale quantum computers will be able to solve the underlying hard problems. In 2021, IBM has released "Eagle", a 127-qubit quantum processor and has a roadmap of 1K-1M+ qubits beyond 2024. NIST has already realized the quantum threat and announced a competition for Post-Quantum Cryptography Standardization Process in 2016. It is currently in round 3 and expected to be finalized with the announcement of KEM and Digital Signature standards by the end of 2022. Apart from algorithmic security, significant attention has been given to implementation attacks such as side-channel and fault attacks. To counter classical Differential Fault Attacks (DFA), which only work for deterministic schemes, the schemes are now offering randomized versions. The goal of this dissertation is to investigate these randomized postquantum signature schemes against fault attacks. The study has identified a number of vulnerabilities in several post-quantum schemes in the NIST competition. We are able to recover the entire key of the LUOV (round 2 finalist) signature scheme in less than 4 hours of Rowhammer attack, followed by our novel bit-tracing algorithm and divide and conquer attack. We have named this hybrid attack QuantumHammer. More recently, we have proposed the "Signature Correction Attack" on the Dilithium signature scheme (round 3 finalist) and successfully reduced its security strength from 128-bit to 81-bit. Rowhammer attack does not require physical access and poses a significant threat to shared cloud servers. The identified vulnerabilities are however generic and can work as long as required faulty signatures are collected using any fault mechanism. The main idea of both bit-tracing and signature correction is to utilize a single faulty signature to mathematically trace back to the fault, revealing the secret key bit. We achieve this by trying to correct a faulty signature for all possible faults in the secret key using the verification algorithm as an oracle. This technique does not need any correct signature counterpart as needed in traditional DFA attacks. In all of our Rowhammer experiments on post-quantum schemes, we have used SPOILER for finding contiguous memory required for double-sided Rowhammer. SPOILER is a hardware bug we discovered in all Intel generations, starting from 1st Gen (2008) of Intel core processors, stemming from the speculative load operations. SPOILER reveals critical physical address information to user space processes which boosts Rowhammer and cache attacks
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Chaos in Memory: A Comprehensive Analysis of Register and Stack Variable Corruption
The past decade has been marked by a multitude of uncovered vulnerabilities within microarchitectures, leading to new attack vectors and spurring an extensive investigation into potential countermeasures. Particularly, the architectural and physical imperfections within DRAM memories have initiated Rowhammer attacks, which provide a pathway to manipulate a victim's memory space via bit flips. While a considerable body of research has proposed measures to mitigate or nullify the effects of Rowhammer, its full exploitability scope remains underexplored. This thesis pushes the frontier by exploring an innovative exploitation of Rowhammer attacks. The approach involves inducing faults in a victim process's stack variables and register values by forcing a task switch. This switch results in the context being stored in the process stack, which, when stored in memory, becomes vulnerable to a Rowhammer attack. Accomplishing such an exploit involves navigating several complex challenges, such as stack pages co-location, ASLR offset randomization, and synchronization. This thesis covers extensive experimentation which resulted in several intriguing findings. Notably, an observed non-random behavior in ASLR offset randomization could potentially facilitate the acceleration of stack co-location. To illustrate the practical ramifications of these findings, this thesis includes examples of their application, such as bypassing SUDO, SSH authentications, MySQL, and other cryptographic libraries. Thus, this work uncovers a new, potent attack vector, underscoring the necessity for ongoing research into potential vulnerabilities and their countermeasures
The Impact of Ideology on Lexical Choices in Literary Translation: A Case Study of A Thousand Splendid Suns
AbstractThis study attempts to discover ideological differences between Hoseini's novelA Thousand Splendid Suns and its two Persian translations, by Ganji and Soleimani and Ghebrai. According to Fairclough, ideology in discourse is encoded in the lexical, grammatical and textual items and changes in these items indicate different ideology. Hence, lexical choices of the source book and the two translations were analyzed based on Fairclough's approach to investigate ideological differences between them. The results of chi-square revealed that there were no ideological difference between the source text and its two translations. Moreover, the translators selected similar vocabularies for representing the ideology of the original author
Application of nonlinear systems in nanomechanics and nanofluids : analytical methods and applications / Davood Domairry Ganji, Sayyid Habibollah Hashemi Kachapi.
Includes bibliographical references and index.xv, 395 pages :With Application of Nonlinear Systems in Nanomechanics and Nanofluids the reader gains a deep and practice-oriented understanding of nonlinear systems within areas of nanotechnology application as well as the necessary knowledge enabling the handling of such systems. The book helps readers understand relevant methods and techniques for solving nonlinear problems, and is an invaluable reference for researchers, professionals and PhD students interested in research areas and industries where nanofluidics and dynamic nano-mechanical systems are studied or applied. The book is useful in areas such as nanoelectronics and bionanotechnology, and the underlying framework can also be applied to other problems in various fields of engineering and applied sciences
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