232 research outputs found
RAM-based fault tolerant state machines for FPGAs
No full textThe paper presents a solution to protect FSM implemented on FPGAs from SEU, exploiting the embedded memories available in modern FPGA devices and a Hamming code for error detection and correction. A fault tolerant FSM architecture is presented, along with a generator to automate the FSM implementation. Experimental results show that this solution is particularly suited especially when FSMs with a large number of outputs are present in the target desig
Introduction. Urban Space as an Interpretative Gaze
No full textThis is the introductory chapter of a volume designed to introduce readers to the interactions and crossovers between culture and the city. The volume in fact intends to investigate urbanity as a cultural form on the basis of a broader and geographically representative collection of case studies. In particular it offers a stimulating range of inter-disciplinary perspectives showing that urban space manifests itself as an interpretative gaze, anchored in human life not just as something to look at but as a cultural form to live in socially.
The essay illustrate the real and imaginary ways that we interact with the cities through the portal of the arts. The author seek to expand and enhance our understanding of how Art, Architecture, Music, Fashion, Film and Media critically engage with urban space and actively contribute to the creation of original cityscapes thus revealing various cultural models of development
Exploiting RAM for fault-tolerant functions in FPGA
No full textWhen realizing a reliable digital system, special attention has to be paid if the target device is an FPGA. In this case, classical fault tolerance techniques are usually not suited to protect the design. This is due to the actual resources used to implement the design, that involves sequential elements even for the combinatorial function and routing. In this paper a method to protect generic functions in FPGA is presented, taking advantage of embedded synchronous memories available on modern FPGAs. As a case study, the implementation of some common functions is proposed along with some optimizations to reduce the use of resources
An Automatic VSLI Implementation of Hopfield ANNs
No full textThe aim of this paper is to present a methodology covering the digital synthesis of a Hopfield neural network. The obtained system is based on a proper pipelined/multiplexed connection among some basic processing elements called pseudo-neurons and is able to support only the recall phase
A new architecture for the automatic design of custom digital neural network
No full textThis brief presents a novel high-performance architecture for implementation of custom digital feed forward neural networks, without on-line learning capabilities. The proposed methodology covers the entire design flow of a neural application, by addressing the internal neuron's structure, the system level organization of the processing elements, the mapping of the abstract neural topology (obtained through simulation) onto the given digital system and eventually the actual synthesis. Experimental results as well as a brief description of the software environment supporting the proposed methodology are also included
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