7,731 research outputs found
ExaNeSt Poster at the HiPEAC 2016 Conference
No full textThis poster aims at introducing the ExaNeSt project. It has been presented during the HiPEAC 2016 Conference, Prague, Czech Republic, 20 January 2016
"Preliminary Dissemination Report", ExaNeSt project Deliverable D7.1
No full textDissemination of research results is an extremely important part of an H2020 European funded project. Effective dissemination will ensure that the project is widely adopted and used across Europe. Project partners are all deeply aware of the need of disseminating project results to those who will use ExaNeSt to build new HPC facilities, and to scientific communities and those SMEs who may ask for and use ExaNeSt powerful platform. The dissemination activities have already encompassed printed and electronic media/publications, workshops, demos, networking, conferences and a project website. The project partners will continue to disseminate ExaNeSt results to a broad audience of data sciences and to SMEs in the emerging HPC market. All the Member States of the EU-28 as well as key non-EU markets will be targeted to ensure the widest possible uptake of the new technologies developed within the project. Existing networks and contacts will be exploited as well as industry associations, consortiums and groups. This document presents the preliminary dissemination activities (in the first 12 months) undertaken against targets set out in the DoA for the ExaNeSt H2020 project.ExaNeSt project Deliverable D7.
"Census of the Applications", ExaNeSt project Deliverable D2.1
No full textIn this document, a survey of scientific and technical applications that could be potentially used in the ExaNeSt project are presented and discussed. The applications are playing a central role in ExaNeSt: they are used to identify a set of initial requirements for the design of the platform, and then they are also used to test the infrastructure during all the implementation phases.
The selected applications represent the state of the art of HPC computing in different disciplines: Astrophysics, Material Science, Climatology, Neuroscience, etc.
The applications described in this document are a preliminary list of software and tools that will be potentially ported and re-engineered during the subsequent phases of the projects. A subset of them will be then identified.
A brief introduction discusses the guidelines used to select the applications. Each application is then presented in detail and all the technical aspects are also outlined. Finally a comparison among them is conducted.ExaNeSt project Deliverable D2.
"Implementation Notes for the Storage and Data Access Infrastructure", ExaNeSt project Deliverable D4.3
No full textIn this deliverable of WP4, D4.3 “Implementation Notes for the Storage and Data Access Infrastructure”, we describe the implementation of each software component and tool that was specified in deliverable D4.2:
Extensions and enhancements to the common I/O path in Linux with focus on two key areas: (i) supporting protected access to storage devices from user space, i.e. direct access to storage with minimal kernel related overheads; and (ii) enhancements to the access path for memory-mapped file access by, amongst others, making use of NVM devices. [FORTH]
Extensions to the BeeGFS parallel file system: Metadata replication mechanisms to handle consistency management and resilience to failures, as well as incorporating those mechanisms in a caching extension. [FHG]
Acceleration mechanisms for Host-to-VM and VM-to-VM interactions that take into account properties of the hardware platform and the unified interconnect. Two main technologies for hardware-assisted virtualisation are considered: (i) use of RDMA capabilities for accessing remote memory from within a virtual machine, and (ii) HPC API remoting to improve the performance of HPC APIs (specifically MPI) for applications that execute as an ensemble of virtual machines. [VOSYS]
The design of a new replication mechanism for analytical databases, and its implementation in MonetDB. This replication scheme has been designed in such a way that it will not only help improving the availability, reliability, performance and scalability of a database server in general, but also help exploiting the ExaNeSt storage infrastructure and the ExaNeSt platform in particular. [MDBS]
Several monitoring and testing tools: the ExaNeSt storage administration and monitoring [INFN]; experiment automation, stress-load and fault injection tools [FORTH]; tests simulating HPC application I/O behaviours [INFN]; and a database profiler [MDBS].
In the storage infrastructure, resilience is mainly addressed by replication mechanisms in the file system. The system’s resilience will be stressed by the stress-load and fault injection tools, while its health is monitored by the monitoring tools. In addition, the system’s resilience level will be evaluated by the HPC and DBMS applications. To achieve the objectives of WP4, the storage and data access infrastructure proposed by ExaNeSt is built upon the following main components: (i) the distributed file system BeeGFS, (ii) Linux data access technologies, (iii) KVM based virtualisation, and (iv) storage system monitoring and administration tools. Moreover, we will use the state-of-the-art HPC applications and analytical databases to guide the design of the envisioned infrastructure and to evaluate and showcase the result.ExaNeSt project Deliverable D4.
The ExaNeSt Project:Interconnects, Storage, and Packaging for Exascale Systems
No full textExaNest is one of three European projects that support a ground-breaking computing architecture for exascale-class systems built upon power-efficient 64-bit ARM processors. This group of projects share an 'everything-close' and 'share-anything' paradigm, which trims down the power consumption - by shortening the distance of signals for most data transfers - as well as the cost and footprint area of the installation - by reducing the number of devices needed to meet performance targets. In ExaNeSt, we will design and implement: (i) a physical rack prototype and its liquid-cooling subsystem providing ultra-dense compute packaging, (ii) a storage architecture with distributed (in-node) non-volatile memory (NVM) devices, (iii) a unified, low-latency interconnect, designed to efficiently uphold desired Quality-of-Service guarantees for a mix of storage with inter-processor flows, and (iv) efficient rack-level memory sharing, where each page is cacheable at only a single node. Our target is to test alternative storage and interconnect options on actual hardware, using real-world HPC applications. The ExaNeSt consortium brings together technology, skills, and knowledge across the entire value chain, from computing IP, packaging, and system deployment, all the way up to operating systems, storage, HPC, big data frameworks, and cutting-edge applications.</p
The next Generation of Exascale-class Systems: the ExaNeSt Project
No full textThe ExaNeSt project started on December 2015 and is funded by EU H2020 research framework (call H2020-FETHPC-2014, n. 671553) to study the adoption of low-cost, Linux-based power-efficient 64-bit ARM processors clusters for Exascale-class systems. The ExaNeSt consortium pools partners with industrial and academic research expertise in storage, interconnects and applications that share a vision of an European Exascale-class supercomputer. Their goal is designing and implementing a physical rack prototype together with its cooling system, the storage non-volatile memory (NVM) architecture and a low-latency interconnect able to test different options for interconnection and storage. Furthermore, the consortium is to provide real HPC applications to validate the system. Herein we provide a status report of the project initial developments.To appear in: the Proceedings of the Euromicro Conference on Digital System Design (DSD 2017), Vienna, Austria, 30 August - 1 September, 201
Next generation of Exascale-class systems: ExaNeSt project and the status of its interconnect and storage development
No full text<p>The ExaNeSt project started on December 2015 and is funded by EU H2020 research framework (call H2020-FETHPC-2014, n. 671553) to study the adoption of low-cost, Linux-based power-efficient 64-bit ARM processors clusters for Exascale-class systems. The ExaNeSt consortium pools partners with industrial and academic research expertise in storage, interconnects and applications that share a vision of an European Exascale-class supercomputer. The common goal is designing and implementing a physical rack prototype together with its cooling system, the non-volatile memory (NVM) architecture and a unified low-latency interconnect able to test different options for network and storage. Furthermore, the consortium goal is to provide real HPC applications to validate the system. In this paper we describe the unified data and storage network architecture, reporting on the status of development of different testbeds and highlighting preliminary benchmark results obtained through the execution of scientific, engineering and data analytics scalable application kernels.</p>
The ExaNeSt Project: Interconnects, Storage, and Packaging for Exascale Systems
No full textS.60-67ExaNest is one of three European projects that support a ground-breaking computing architecture for exascale-class systems built upon power-efficient 64-bit ARM processors. This group of projects share an 'everything-close' and 'share-anything' paradigm, which trims down the power consumption - by shortening the distance of signals for most data transfers - as well as the cost and footprint area of the installation - by reducing the number of devices needed to meet performance targets. In ExaNeSt, we will design and implement: (i) a physical rack prototype and its liquid-cooling subsystem providing ultra-dense compute packaging, (ii) a storage architecture with distributed (in-node) non-volatile memory (NVM) devices, (iii) a unified, low-latency interconnect, designed to efficiently uphold desired Quality-of-Service guarantees for a mix of storage with inter-processor flows, and (iv) efficient rack-level memory sharing, where each page is cacheable at only a single node . Our target is to test alternative storage and interconnect options on actual hardware, using real-world HPC applications. The ExaNeSt consortium brings together technology, skills, and knowledge across the entire value chain, from computing IP, packaging, and system deployment, all the way up to operating systems, storage, HPC, big data frameworks, and cutting-edge applications
SHui open data research platform
No full textData collected and revised by individual instutions of the Shui-Consortium. Publication by the EU-China Consortium SHui.For each data-file, the author (institution) of the file is given as “operator”.-- At project end, June 30th, 2022.-- For each data-file, the author/data owner for citation is given as “operator” and “contact”.-- Plot data as .csv; catchment data ad libitum.Spatial situation data: Plot data and catchment data available; country, latitude, and longitude coordinates given.-- Temporal situation data: Long-term and single-season data available. Start and end date for each data file given.CC BY-SA. No embargo. The release on the Shui download site and CSIC repository implies expiration of any embargo delivered by the data owner.Project Co-ordinators: Dr. Jose Alfonso Gómez Calero (Instituto de Agricultura Sostenible (IAS-CISC), Dr. Weifeng Xu (Fujian Agriculture and Forest University, FAFU).This data set contains data from the SHui open-data platform for sharing long-term agricultural experiments aimed to optimizing yield and soil and water. Data and additional material are available under https://shui.boku.ac.at/shui/public/startAlphanumeric data measured at hydrologic and agronomical experiments (e.g., plant development, soil properties, hydrology, erosion, management).Further information on the data, project, partners, and publications under https://www.shui-eu.org/EU-China Consortium SHui: European Union Project 773903 and Chinese MOST.Peer reviewe
Next generation of Exascale-class systems:ExaNeSt project and the status of its interconnect and storage development
No full textThe ExaNeSt project started on December 2015 and is funded by EU H2020 research framework (call H2020-FETHPC-2014, n. 671553) to study the adoption of low-cost, Linux-based power-efficient 64-bit ARM processors clusters for Exascale-class systems. The ExaNeSt consortium pools partners with industrial and academic research expertise in storage, interconnects and applications that share a vision of an European Exascale-class supercomputer. The common goal is designing and implementing a physical rack prototype together with its cooling system, the non-volatile memory (NVM) architecture and a unified low-latency interconnect able to test different options for network and storage. Furthermore, the consortium goal is to provide real HPC applications to validate the system. In this paper we describe the unified data and storage network architecture, reporting on the status of development of different testbeds and highlighting preliminary benchmark results obtained through the execution of scientific, engineering and data analytics scalable application kernels.</p
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