1,720,975 research outputs found
An UMTS ΣΔ fractional synthesizer with 200 kHz bandwidth and -128 dBc/Hz @ 1 MHz using spurs compensation and linearization techniques
No full textThis paper describes a general study on spurs generation in fractional synthesis and techniques for their reduction. This theory has been verified with the realization of two IC prototypes fabricated in 0.18 μm CMOS, targeting UMTS-WCDMA specifications, both with a frequency resolution of 35 Hz. The first one is a fully integrated (1.9×1.6 mm2) 2.1 GHz ΣΔ synthesizer burning 19 mW, with 600 kHz 3 dB closed loop bandwidth. Its spur performance is limited by non-linear effects. This limitation has been overcome by linearization techniques implemented in a second chip with external VCO and loop filter. This synthesizer achieves -128 dBc/Hz @ 1 MHz offset with a 200 kHz 3 dB closed loop bandwidth
A 700-kHz bandwidth Sigma-Delta fractional synthesizer with spurs compensation and linearization techniques for WCDMA applications
No full textA ΣΔ fractional-N frequency synthesizer targeting WCDMA receiver specifications is presented. Through spurs compensation and linearization techniques, the PLL bandwidth is significantly extended with only a slight increase in the integrated phase noise. In a 0.18-μm standard digital CMOS technology a fully integrated prototype with 2.1-GHz output frequency and 35 Hz resolution has an area of 3.4 mm2 PADs included, and it consumes 28 mW. With a 3-dB closed-loop bandwidth of 700 kHz, the settling time is only 7 μs. The integrated phase noise plus spurs is -45 dBc for the first WCDMA channel (1 kHz to 1.94 MHz) and -65 dBc for the second channel (2.5 to 6.34 MHz) with a worst case in-band (unfiltered) fractional spur of -60 dBc. Given the extremely large bandwidth, the synthesizer could be used also for TX direct modulation over a broad band. The choice of such a large bandwidth, however, still limits the spur performance. A slightly smaller bandwidth would fulfill WCDMA requirements. This has been shown in a second prototype, using the same architecture but employing an external loop filter and VCO for greater flexibility and ease of testing
A 19mW 2.2GHz Fully Integrated CMOS Sigma Delta Fractional Synthesiser With 35Hz Frequency Step and Quantization Noise Compensation
No full textA fully integrated 0.18μm CMOS ΣΔ fractional synthesizer targeting 3G wireless terminals applications is presented. This work is a practical example of a more general study on frequency fractional synthesis. A simple linear model of the system is presented and used to simulate different ΣΔ modulators topologies and to evaluate the effects of circuits non-idealities particularly on output spurious tones. Phase Frequency Detector (PFD) and Charge Pump (CP) non-linearity effects are analysed in details, the obtained results are confirmed by measurement. Solutions to overcome these limitations are given. At last, a ΣΔ quantization noise compensation technique is presented allowing to break the trade-off between Phase Locked Loop (PLL) bandwidth and high frequency noise regrowth
A 3GHz fractional all digital PLL with a 1.8MHz bandwidth implementing spur reduction techniques
No full textDigital implementation of analog functions is becoming
attractive in CMOS ICs, given the low supply voltage of
ultra-scaled processes. Particularly, all-digital PLLs are being
considered for RF frequency synthesis. However, they suffer from
intrinsic deficiencies making them inferior to traditional analog
solutions. The investigation in this paper shows that in-band
output spurs, the major shortcoming of wideband divider-less
ADPLLs with respect to analog fractional PLLs, are intrinsic and
due to the finite resolution of the time-to-digital converter (TDC),
even assuming perfect quantization and linearity. Moreover, even
if the conceptual spur level is arbitrarily reduced by increasing
the TDC resolution, TDC nonlinearities can cause a significant
spur re-growth. This paper proposes two techniques to reduce the
gap between all-digital and analog implementations of wideband
fractional PLLs. These techniques have been applied to a 3 GHz
ADPLL, whose bandwidth is programmable from 300 kHz to
1.8 MHz, operating from a 25 MHz reference signal. The test
chip features more than 10 dB of worst in-band spur reduction
when both corrections are active, for a worst-case in-band spur of
45 dBc at a bandwidth of 1.8 MHz and an in-band noise floor of
101 dBc/Hz. The chip core occupies 0.4 mm in 65 nm CMOS
technology, and consumes less than 10 mW from a 1.2 V supply
A 0.86 – 2.4 GHz Fractional Synthesizer with Spur Compensation and Linearization Techniques for Multi-standard Cellular Transceivers
No full textGoing Beyond Counting First Authors in Author Co-citation Analysis
Full text linkThe present study examines one of the fundamental aspects of author co-citation analysis (ACA) - the way co-citation
counts are defined. Co-citation counting provides the data on which all subsequent statistical analyses and mappings
are based, and we compare ACA results based on two different types of co-citation counting - the traditional type that
only counts the first one among a cited work's authors on the one hand and a non-traditional type that takes into
account the first 5 authors of a cited work on the other hand. Results indicate that the picture produced through this non-traditional author co-citation counting contains more coherent author groups and is therefore considerably clearer. However, this picture represents fewer specialties in the research field being studied than that produced through the traditional first-author co-citation counting when the same number of top-ranked authors is selected and analyzed. Reasons for these effects are discussed
Reconfigurable VCOs and Synthesizers
No full textInvited talk sui VCO e sintetizzatori di frequenza riconfigurabili per terminali wireless portatili
- …
