17 research outputs found
Design of an Efficient Parallel Comparator Architecture for Low Power Delay Product
Full text linkA binary comparator architecture is proposed in this work for static logic to achieve both low-power and high-performance operations. It also presents a detailed timing performance and power analysis of various state-of-the-art comparator designs. The main advantages of this design are its high speed and power efficiency maintained over a wide range of operands size, which is useful at low-input data activity environments. The proposed circuit design uses minimum fan-in and fan-out logic gates for achieving high speed and low power dissipation. Utilizing a 2-bit binary comparator circuit with minimum fan-in and fan-out of logic gates (NAND-NOR), the architecture of a parallel binary comparator is proposed for higher input operands by using a low radix multiplexer and priority encoder. Further, to decrease the size of the multiplexer and priority encoder by two times, a general architecture is also proposed by using a 4-bit binary comparator to reduce its complexity. The proposed circuits are optimized in terms of the power consumption and delay, which are due to low load capacitance, low leakages, and reduced dynamic power dissipation. Each of the proposed circuits has its own merits in terms of speed, power consumption, Power-Delay Product (PDP). Its synthesis is done on 180 nm as well as 90 nm CMOS technology using the Cadence tool. The physical layout of the proposed architecture using a 90 nm CMOS process (GPDK process) is also obtained
Impact of Work Function Tunability on Thermal and RF Performance of P-type Window based Junctionless Transistor
Full text linkThe choice of gate metal technology for junctionless transistors needs to have diverse characteristics as metals have distinct work functions and hence, they show incompatibility while tailoring threshold of the device. In such a scenario, bimetallic stacked gate can be a promising candidate to present wide range of tunable work functions required for nano-regime junctionless transistors. This paper explores the electronic phenomena occurring at metal-metal interface and the impact of Platinum (Pt)/Titanium (Ti) bimetallic stacked gate-based work function tunability on the RF and thermal performances of p-type window-based Silicon on Insulator Junctionless Transistor (SOI JLT) using numerical simulator SILVACO ATLAS. The parameters considered for performance evaluation are ON-state current (I_{ON}), OFF-state current (I_{OFF}), I_{ON}/I_{OFF} ratio, transconductance (g_m),\linebreak cutoff frequency (f_T), Transconductance Frequency Product (TFP), Intrinsic Gate Delay (IGD), intrinsic gain (A_V), and Global Device Temperature (GDT). The g_m, f_T, TFP, A_V and GDT improve for modified over conventional in the ON state at higher work function, while IGD improves at lower work function. The improvements of 11.7% and 2.21% are obtained in maximum g_m and f_T, respectively, for modified transistor over conventional. The findings suggest that bimetallic stacked gate modified SOIJLT is a better option than conventional for low-power RF application
Information needs of women self help groups: an assessment
Full text linkThe most popular model of micro credit in India is that of self-help groups (SHGs). A qualitative study of SHG interventions in Andhra Pradesh and Gujarat undertaken by Nirantar, a Centre for Gender and Education, offers insights into the micro-credit phenomenon through voices of women who are part of SHGs. Mostly women are the beneficiaries of this micro credit system. A district-level official linked to a national level SHG programme sponsored by the ministry of rural development explained why the programme focused on women. “Women cannot go anywhere, they can be located easily; they cannot run away leaving their homes; they can be easily persuaded to repay as they feel shame more quickly and consider non-repayment as a betrayal of family honour”
Archi-texture: meditations on the mediations of dwelling
Full text linkThis thesis is an inter-disciplinary and inter- cultural exploration of home as understood as the place in which we usually live. Empirical research in an Australian suburb and an Indian town provide the fabric from which cultural studies engages with phenomenology to produce a design used to cut and style this exploration. Motivated by an interest in what threads contribute to the weave of contemporary household dwelling, this thesis revisits the two questions used by Heidegger to frame his essay 'Building Dwelling Thinking': What is it to dwell? and How does building belong to dwelling? It is an inquiry committed to its respondents as bearers and representatives of 'structures of feeling' circulating within the socio-cultural milieu or habitus in which they live and engage with the idea of 'home'. This inquiry offers an exploration of the chief constituent mediums of home which I call its 'archi-texture'. As such, it looks at location, physical and material attributes, domestic technology and household membership as framed by the presence or absence of a family. This thesis is almost certainly the only example of an empirically grounded examination of Heidegger?s ontological exposition of dwelling. Hence I position it as a meditation on the mediations of dwelling rather than a judgmental critique, although in no sense do I believe it to be either a dispassionate position nor an impartial digest of the research material
