1,721,047 research outputs found
A 2Mbit Digital in-Memory Computing Matrix-Vector Multiplier for DNN Inference supporting flexible bit precision and matrix size achieving 612 binary TOPS/W
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Vertical M1 routing-aware detailed placement for congestion and wirelength reduction in sub-10nm nodes.
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Computation-skip error mitigation scheme for power supply voltage scaling in recursive applications
No full textMILP-based optimization of 2-D block masks for timing-aware dummy segment removal in self-aligned multiple patterning layouts
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Memory Devices and A/D Interfaces: Design Trade-offs in Mixed-Signal Accelerators for Machine Learning Applications
Full text linkThis tutorial focuses on memory elements and analog/digital (A/D) interfaces used in mixed-signal accelerators for deep neural networks (DNNs) in machine learning (ML) applications. These very dedicated systems exploit analog in-memory computation (AiMC) of weights and input activations to accelerate the DNN algorithm. The co-optimization of the memory cell storing the weights with the peripheral circuits is mandatory for improving the performance metrics of the accelerator. In this tutorial, four memory devices for AiMC are reported and analyzed with their computation scheme,
including the digital-to-analog converter (DAC). Moreover, we review analog-to-digital converters (ADCs) for the quantization of the AiMC results, focusing on the design trade-offs of the different topologies given by the context
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