37 research outputs found
A Method and Criterion for Repetitive Surge Current in Silicon Carbide Schottky Diodes
No full textThe need for efficient power-conversion systems in renewable energy, electric vehicles, and industrial power applications has motivated the development of wide-bandgap power semiconductor devices, such as the SiC Schottky diode. An important parameter that establishes the reliability of these high-power devices is their repetitive forward surge current, which ensures robust circuit designs that can withstand high current conditions without damage or failure. However, there is no consistent measurement method to determine this parameter for SiC Schottky diodes, and manufacturers that provide this parameter have no clear indication of the methodology used to obtain the presented value. In this work, we propose a measurement method and a user-focused criterion for the repetitive peak forward surge current, which also ensures the junction temperature does not exceed the maximum device rating. We demonstrate the need for this criterion by comparing measured surge-current performance of commercially available diodes with two different structures—merged PN Schottky diodes and homogenous Schottky-barrier diodes—designed with three different blocking voltages: 650 V, 1200 V, and 1700 V.Full Tex
Characterization of Active Near Interface Traps in 4H-SiC MOS Devices
No full textIn the past years, silicon carbide (SiC) has established itself among manufacturers as a preferred choice for the fabrication of power semiconductor devices. Commercially available SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) have surpassed the theoretical limits of Si MOSFETs, but they still must address a few issues to reach the theoretical limits of SiC. A key challenge is to improve the performance of SiC MOSFETs by increasing the average channel-carrier mobility. The reason for reduced channel-carrier mobility is a high density of electrically-active defects at the SiC-SiO2 interface. Hence, accurate characterisation of the SiC-SiO2 interface is essential for the advancement of SiC power devices.
This thesis focuses on the defects responsible for the performance degradation of SiC MOSFETs due to trapping of electrons from the MOSFET channel. After a brief introduction to the research project, a systematic review of electrically-active defects at the SiC-SiO2 interface is performed. The defects are classified according to their physical locations and energy positions, and their impact on the SiC MOSFET is studied. Additionally, the study investigates the existing measurement techniques and their limitations. [...]Thesis (PhD Doctorate)Doctor of Philosophy (PhD)School of Eng & Built EnvScience, Environment, Engineering and TechnologyFull Tex
Electrically Active Defects in SiC Power MOSFETs
No full textThe performance and reliability of the state-of-the-art power 4H-SiC metal–oxide–semiconductor field-effect transistors (MOSFETs) are affected by electrically active defects at and near the interface between SiC and the gate dielectric. Specifically, these defects impact the channel-carrier mobility and threshold voltage of SiC MOSFETs, depending on their physical location and energy levels. To characterize these defects, techniques have evolved from those used for Si devices to techniques exclusively designed for the SiC MOS structure and SiC MOSFETs. This paper reviews the electrically active defects at and near the interface between SiC and the gate dielectric in SiC power MOSFETs and MOS capacitors. First, the defects are classified according to their physical locations and energy positions into (1) interface traps, (2) near interface traps with energy levels aligned to the energy gap, and (3) near-interface traps with energy levels aligned to the conduction band of SiC. Then, representative published results are shown and discussed for each class of defect
Active Defects in 4H–SiC MOS Devices
No full textThe research findings presented in this thesis have provided several key contributions towards a better understanding of the SiC–SiO2 interface in SiC MOS structures. The electrically active defects directly responsible for degrading the channel-carrier mobility in 4H–SiC MOSFETs have been identified and a novel technique to detect these defects in 4H–SiC MOS capacitors has been proposed and experimentally demonstrated. With a better understanding of defects at the SiC–SiO2 interface two alternative gate oxide growth processes have been proposed to overcome the practical limitations associated with current NO-nitridation techniques in high-volume, production based oxidation furnaces. This work therefore contributes to the wider research effort towards improving the performance of SiC MOSFETs in several ways. The following paragraphs summarise the key conclusions that have been obtained as a result of this study.
Electrically Active Defects and the Channel-Carrier Mobility (Chapter 3)
A critical review of defects at the SiC–SiO2 interface exposed a few key discrepancies in both the current understanding of the dominant defects responsible for channel-carrier mobility degradation in 4H–SiC MOSFETs and in the current approach to characterise and evaluate the SiC–SiO2 interface. Firstly, it was recognised that the Shockley-Read-Hall statistical model, based on thermally activated transport for traps spatially located at the semiconductor-oxide interface, cannot be directly applied to describe the transfer mechanism between free conduction band electrons and the shallow NITs near EC. This implication tends to suggest that the NITs near EC in SiC MOS structures cannot be accurately examined using traditional MOS characterisation techniques that are based on this statistical model. Secondly, in accordance with the studies conducted by Saks et. al. [1-3], it was realized that channel-carrier mobility degradation in 4H–SiC MOSFETs is primarily due to the significantly reduced free electron density in the inversion channel. In light of this understanding, the interfacial defects that actively trap channel electrons under strong inversion conditions were considered to be dominant in these devices as opposed to the NITs near EC that are typically examined using conventional MOS characterisation techniques on N-type MOS capacitors in depletion. To further support this hypothesis, a theoretical analysis of the inversion carrier concentration using the charge sheet model was conducted to demonstrate that the NITs with energy levels corresponding to strong inversion are of key importance to the channel-carrier mobility.Thesis (PhD Doctorate)Doctor of Philosophy (PhD)Griffith School of EngineeringScience, Environment, Engineering and TechnologyFull Tex
A Figure of Merit for Selection of the Best Family of SiC Power MOSFETs
No full textThis paper proposes a criterion to select the best family of commercial SiC power metal–oxide–semiconductor field-effect transistors (MOSFETs) that provides the highest quality and reliability. Applying a recently published integrated-charge method, a newly proposed figure of merit is correlated to the density of near-interface traps that degrade the quality and reliability of SiC MOSFETs. The applicability of the proposed figure of merit is experimentally demonstrated with the most widely used and commercially available planar and trench MOSFETs from different manufacturers
Impact of nitridation on the active near-interface traps in gate oxides on 4H-SiC
No full textIn this paper we have implemented a recently proposed direct-measurement technique to characterize near-interface oxide traps (NITs) in SiC MOS capacitors with gate oxides obtained by four different processes. This measurement technique enables characterization of NITs with energy levels above the bottom of the conduction band, which are active in the accumulation mode of MOS capacitors on N-type SiC and in the strong inversion of N-channel MOSFETs. The measurements revealed that annealing in nitric oxide of thermally grown oxides in dry oxygen removes NITs that are further away from the SiC surface, but it leaves a defect with energy levels located between 0.13 eV and 0.23 eV above the bottom of conduction band. The oxides grown in pure nitric oxide exhibit NITs with energy levels above 0.2 eV. The measurements also show that low-temperature oxide deposition and subsequent annealing in nitric oxide resulted in the lowest density of NITs.No Full Tex
A method for characterizing near-interface traps in SiC metal–oxide–semiconductor capacitors from conductance–temperature spectroscopy measurements
No full textThe state-of-the-art technology for gate oxides on SiC involves the introduction of nitrogen to reduce the density of interface defects. However, SiC metal-oxide-semiconductor (MOS) field-effect transistors still suffer from low channel mobility even after the nitridation treatment. Recent reports have indicated that this is due to near-interface traps (NITs) that communicate with electrons in the SiC conduction band via tunneling. In light of this evidence, it is clear that conventional interface trap analysis is not appropriate for these defects. To address this shortcoming, we introduce a new characterization method based on conductance-temperature spectroscopy. We present simple equations to facilitate the comparison of different fabrication methods based on the density and location of NITs and give some information about their origin. These techniques can also be applied to NITs in other MOS structures.</p
Detection of near-interface traps in NO annealed 4H-SiC metal oxide semiconductor capacitors combining different electrical characterization methods
No full textFast near-interface (NI) traps have recently been suggested to be the main cause for poor inversion channel mobility in nitrided SiC metal-oxide-semiconductor-field-effect-transistors. Combining capacitance, conductance, and thermal dielectric relaxation current (TDRC) analysis at low temperatures of nitrided SiC MOS capacitors, we observe two categories of fast and slow near-interface traps at the SiO2/4H-SiC interface. TDRC reveals a suppression of slow near-interface traps after nitridation. Capacitance and conductance analysis reveals a high density of fast NI traps close to the SiC conduction band edge that are enhanced by nitridation. The very fast response of NI traps prevents them from detection using TDRC or deep level transient spectroscopy. (C) 2022 Author(s).Funding Agencies|Icelandic Centre for Research (Rannis) [185412-052]; University of Iceland Research Fund</p
Quantified density of performance-degrading near-interface traps in SiC MOSFETs
No full textCharacterization of near-interface traps (NITs) in commercial SiC metal-oxide-semiconductor field-effect transistors (MOSFETs) is essential because they adversely impact both performance and reliability by reducing the channel carrier mobility and causing threshold-voltage drift. In this work, we have applied a newly developed integrated-charge technique to measure the density of NITs that are active in the above-threshold region of commercial SiC MOSFETs. The results demonstrate that NITs trap about 10% of the channel electrons for longer than 500 ns.Full Tex
Comparison of the Performance-Degrading Near-Interface Traps in Commercial SiC MOSFETs
No full textThis paper presents a comparison of the density of performance-degrading near-interface traps (NITs) in the most commonly available 1200 V commercial N-channel SiC power metal–oxide–semiconductor field-effect transistors (MOSFETs). A recently developed integrated-charge technique was used to measure the density of NITs with energy levels aligned to the conduction band, which degrade MOSFET’s performance by capturing and releasing electrons from the channel biased in the strong-inversion condition. Trench MOSFETs of one manufacturer have lower densities of these NITs in comparison to MOSFETs with the planar gate structure, corresponding to observed higher channel-carrier mobility in trench MOSFETs. Different response-time distributions were also observed, corresponding to different spatial location of the measured NITs.Full Tex
