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An analytical model of the potential barrier for the ID-VGS curves calculation of 4H-SiC Bipolar JFETs
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On the analogy of the potential barrier of trenched JFET and JBS devices
No full text4H–SiC Trench Junction Barrier Schottky (TJBS) diodes are good candidates for ultra–high voltage applications when low doped epilayers are required. In that case, electric fields of p+–n junctions deeply extend under the Schottky contact which may induce a potential barrier at thermal equilibrium condition, similarly to what happens into the channel of Trench Junction Field Effect Transistors (TJFET). For the first time, the analogy between potential barriers of 4H–SiC TJBS and TJFET devices is in depth investigated by using an original analytical model. For both devices, the model allows an accurate analysis of the potential barrier height into the channel as a function of the channel width, of the p+–region and trench depths, of the doping concentration and of the reverse voltage. Since the model is also capable to calculate the reverse diode current of TJBS until the vanishing of the potential barrier, it is used to explain the intrinsic differences of devices as the non–monotonic reverse behaviour of TJBs with the depth of the trenched mesa. The accuracy of the model is verified by comparisons with numerical simulations. The model makes a further contribution to the understanding of the role of p+–regions on TJBS performance
A model of the off-behaviour of 4H–SiC power JFETs
No full textA physical model of the off-behaviour of Vertical Junction Field Effect Transistors (VJFETs) up to their blocking voltage limit is presented. Since the drain current, ID, of these devices strongly depends on the amount of the voltage barrier occurring in the channel, the model is capable to describe the drain voltage dependence of the voltage barrier and of ID from VDS = 0 V up to maximum VDS value (kV) sustained from device and to describe the effects of geometry and doping of channel. The accuracy of the model is proven by comparing the ID–VDS curves with numerical simulations of devices designed with different gate depth, channel width, and epilayer thickness. The agreement between model, numerical simulations and literature data confirms the capability of model to describe the ID–VDS curves of devices having a pentode or triode like behaviour
Weighted Partitioning for Fast Multiplier-less Multiple Constant Convolution Circuit
No full textA new radix-3 partitioning method of natural
numbers, derived by the weight partition theory, is employed to
build a multiplier-less circuit well-suited for multimedia filtering
applications. The partitioning method allows to conveniently pre-
multiply 32 bit floating-point (FP32) filter coefficients with the
smallest set of parts composing an unsigned integer input. In this
way, similarly to the Distributed Arithmetic, shifters and
recoding circuitry, typical of other well-known multiplier
circuits, are completely substituted with simplified floating-point
adders. Compared to the existent literature, targeted to both
FPGA and std_cell technology, the proposed solution achieves
state-of-the-art performances in terms of elaboration velocity,
achieving a critical path delay of about 2 ns both on a Xilinx
Virtex 7 and with CMOS 90nm std_cells
Design of an offset-tolerant voltage sense amplifier bit-line sensing circuit for SRAM memories
No full textThe design of a new bit-line sensing scheme of SRAM memories is presented, which combines offset cancellation and compensation solutions. FCMOS inverters, brought to operate in their maximum gain region, are used to compensate the systematic offset of the sense amplifier and reduce the sensing delay. Systematic offset of the inverter amplifiers is cancelled by means of equalising feedback connections. A simulation analysis in Cadence environment and TSMC PDK demonstrates the very good potential of the proposed solution when it is compared with the recent and the established literature
A Quasi-One-Dimensional Model of the Potential Barrier and Carrier Density in the Channel of Si and 4H-SiC BSITs
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