1,720,965 research outputs found

    Susceptibility to EMI of a Battery Management System IC for electric vehicles

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    The susceptibility to Electromagnetic Interference (EMI) of Battery Management Systems (BMSs) for Li-ion and LiPo battery packs employed in emerging electric and hybrid electric vehicles is investigated in this paper. To this purpose, a specif c test board is developed to experimentally assess the EMI susceptibility of a BMS front-end integrated circuit by direct power injection (DPI) and radiated susceptibility measurements. Experimental results are discussed highlighting different EMI-induced failure mechanisms observed during the tests

    Detection and Suppression of Intentional EMI Attacks to Smart Speakers

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    A new digital technique to detect and suppress intentional electromagnetic interference (IEMI) attacks on smart speakers (SSs) without disrupting their nominal operation during the attack is proposed in this article. The effectiveness of the proposed approach is verified by experiments on a proof-of-concept SS prototype equipped with an artificial intelligence speech recognition algorithm. Thanks to the proposed suppression technique, the power of malicious signal in the audio band is suppressed by 19 dB, thus effectively preventing the execution of malicious commands in more than 99.6% of the cases under IEMI attacks of up to 5 dBm injected RF power in 10-100 MHz bandwidth. Under the same test conditions, the proposed detection technique, operating independently from the suppression method, makes it possible to successfully identify IEMI attacks in more than 99.8% of the cases. Experimental results also show the proper recognition of nominal commands while IEMI attacks are performed

    Fully Synthesizable Low-Area Digital-to-Analog Converter With Graceful Degradation and Dynamic Power-Resolution Scaling

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    In this paper, a fully synthesizable digital-to-analog converter (DAC) is proposed. Based on a digital standard cell approach, the proposed DAC allows very low design effort, enables digital-like shrinkage across CMOS generations, low area at down-scaled technologies, and operation down to near-threshold voltages. The proposed DAC can operate at supply voltages that are significantly lower and/or at clock frequencies that are significantly greater than the intended design point, at the expense of moderate resolution degradation. In a 12-bit 40-nm testchip, graceful degradation of 0.3bit/100mV is achieved when V_DD is over-scaled down to 0.8V, and 1.4bit/100mV when further scaled down to 0.6V. The proposed DAC enables dynamic power-resolution tradeoff with 3X (2X) power saving for 1-bit resolution degradation at iso-sample rate (iso-resolution). A 12-bit DAC testchip designed with a fully automated standard cell flow in 40nm consumes 55μW at 27kS/s (9.1μW at 13.5kS/s) at a compact area of 500μm^2 and low voltage of 0.55V

    Relaxation Digital-to-Analog Converters Featuring Self-Calibration and Parasitics-Induced Error Suppression in 180-nm CMOS

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    The design and the silicon characterization of two mostly digital, low-voltage, energy- and area-efficient Relaxation Digital-to-Analog Converters (ReDACs) in 180nm featuring digital self-calibration and parasitics-induced error suppression are presented and compared in this paper. The first design is a single-ended ReDAC (SE-ReDAC) and operates at 880kS/s with a 10-bit resolution, while the second is based on a differential ReDAC (Diff-ReDAC) architecture and operates at 100kS/s with a 13-bit resolution. The SE-ReDAC testchip in 180nm occupies just 5,030 μ m2 and operates with a supply voltage ranging from 0.6V to 1V. Experimental results at 0.65V reveal a 72.18dB-SFDR, a 65.59dB-THD and a 56.09dB SINAD, resulting in 9.02ENOB, with a power dissipation of just 3.3 μ W, achieving a competitive energy-efficiency (area-normalized energy efficiency) figure of merit FOM (FOMA) of 166dB (175dB). On the other hand, the 180-nm Diff-ReDAC testchip occupies 7,800μ m2 and operates in a supply voltage range from 0.45V to 1V, while achieving a 77.81dB-SFDR, a 77.52dB-THD and a 65.82dB-SINAD (10.64ENOB) at 0.6V supply with a power consumption of just 880nW, leading to a very competitive FOM (FOMA) of 172dB (178dB)

    Design of Relaxation Digital-to-Analog Converters for Internet of Things Applications in 40nm CMOS

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    A 10-bit-400kS/s and a 10-bit-2MS/s Relaxation Digital to Analog Converters (ReDAC) in 40nm are presented in this paper. The two ReDACs operate from a 600mV power supply, occupy a silicon area of less than 1,000um^2. The first/second DAC achieve a maximum INL of 0.33/0.72 LSB and a maximum DNL of 0.2/1.27 LSB and 9.9/9.4 ENOB based on post-layout simulations. The average energy per conversion is less than 1.1/0.73pJ, corresponding to a FOM of 1.1/1.08 fJ/(conv. step), which make them well suited to Internet of Things (IoT) applications. (PDF) Design of Relaxation Digital-to-Analog Converters for Internet of Things Applications in 40nm CMOS. Available from: https://www.researchgate.net/publication/336552301_Design_of_Relaxation_Digital-to-Analog_Converters_for_Internet_of_Things_Applications_in_40nm_CMOS [accessed Nov 16 2019]

    Going Beyond Counting First Authors in Author Co-citation Analysis

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    The present study examines one of the fundamental aspects of author co-citation analysis (ACA) - the way co-citation counts are defined. Co-citation counting provides the data on which all subsequent statistical analyses and mappings are based, and we compare ACA results based on two different types of co-citation counting - the traditional type that only counts the first one among a cited work's authors on the one hand and a non-traditional type that takes into account the first 5 authors of a cited work on the other hand. Results indicate that the picture produced through this non-traditional author co-citation counting contains more coherent author groups and is therefore considerably clearer. However, this picture represents fewer specialties in the research field being studied than that produced through the traditional first-author co-citation counting when the same number of top-ranked authors is selected and analyzed. Reasons for these effects are discussed

    Variations on the Author

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    “Variations on the Author” discusses two of Eduardo Coutinho’s recent films (Um Dia na Vida, from 2010, and Últimas Conversas, posthumously released in 2015) and their contribution to the general question of documentary authorship. The director’s filmography is characterized by a consistent yet self-effacing form of authorial self-inscription: Coutinho often features as an interviewer that rather than express opinions propels discourses; an interviewer that is good at listening. This mode of self-inscription characterizes him as an author who is not expressive but who is nonetheless markedly present on the screen. In Um Dia na Vida, however, Coutinho is completely absent form the image, while Últimas Conversas, on the contrary, includes a confessional prologue that moves the director from the margins to the center of his films. This article examines the ways in which these works stand out in the filmography of a director who offers new insights into the notion of cinematic authorship

    Appropriate Similarity Measures for Author Cocitation Analysis

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    We provide a number of new insights into the methodological discussion about author cocitation analysis. We first argue that the use of the Pearson correlation for measuring the similarity between authors’ cocitation profiles is not very satisfactory. We then discuss what kind of similarity measures may be used as an alternative to the Pearson correlation. We consider three similarity measures in particular. One is the well-known cosine. The other two similarity measures have not been used before in the bibliometric literature. Finally, we show by means of an example that our findings have a high practical relevance.information science;Pearson correlation;cosine;similarity measure;author cocitation analysis
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