1,721,011 research outputs found
Going Beyond Counting First Authors in Author Co-citation Analysis
Full text linkThe present study examines one of the fundamental aspects of author co-citation analysis (ACA) - the way co-citation
counts are defined. Co-citation counting provides the data on which all subsequent statistical analyses and mappings
are based, and we compare ACA results based on two different types of co-citation counting - the traditional type that
only counts the first one among a cited work's authors on the one hand and a non-traditional type that takes into
account the first 5 authors of a cited work on the other hand. Results indicate that the picture produced through this non-traditional author co-citation counting contains more coherent author groups and is therefore considerably clearer. However, this picture represents fewer specialties in the research field being studied than that produced through the traditional first-author co-citation counting when the same number of top-ranked authors is selected and analyzed. Reasons for these effects are discussed
Variations on the Author
Full text link“Variations on the Author” discusses two of Eduardo Coutinho’s recent films (Um Dia na Vida, from 2010, and Últimas Conversas, posthumously released in 2015) and their contribution to the general question of documentary authorship. The director’s filmography is characterized by a consistent yet self-effacing form of authorial self-inscription: Coutinho often features as an interviewer that rather than express opinions propels discourses; an interviewer that is good at listening. This mode of self-inscription characterizes him as an author who is not expressive but who is nonetheless markedly present on the screen. In Um Dia na Vida, however, Coutinho is completely absent form the image, while Últimas Conversas, on the contrary, includes a confessional prologue that moves the director from the margins to the center of his films. This article examines the ways in which these works stand out in the filmography of a director who offers new insights into the notion of cinematic authorship
Appropriate Similarity Measures for Author Cocitation Analysis
Full text linkWe provide a number of new insights into the methodological discussion about author cocitation analysis. We first argue that the use of the Pearson correlation for measuring the similarity between authors’ cocitation profiles is not very satisfactory. We then discuss what kind of similarity measures may be used as an alternative to the Pearson correlation. We consider three similarity measures in particular. One is the well-known cosine. The other two similarity measures have not been used before in the bibliometric literature. Finally, we show by means of an example that our findings have a high practical relevance.information science;Pearson correlation;cosine;similarity measure;author cocitation analysis
Dispelling the Myths Behind First-author Citation Counts
Full text linkWe conducted a full-scale evaluative citation analysis study of scholars in the XML research field to explore just how different from each other author rankings resulting from different citation counting methods actually are, and to demonstrate the capability of emerging data and tools on the Web in supporting more realistic citation counting methods. Our results contest some common arguments for the continued
use of first-author citation counts in the evaluation of scholars, such as high correlations between author rankings by first-author citation counts and other citation
counting methods, and high costs of using more realistic citation counting methods that are not well-supported by the ISI databases. It is argued that increasingly available digital full text research papers make it possible for citation analysis studies to go beyond what the ISI databases have directly supported and to employ more
sophisticated methods
Improved software pipelining for superscalar architectures
No full textAlthough instruction scheduling is an scNP-complete problem (27), many techniques have been developed to improve pipelining efficiency. Among them, several were proposed for scVLIW machines, and were shown to be efficient and extendible to superscalar architectures. However the available resources on a superscalar can vary significantly. Our goal for this thesis is to improve the effectiveness of software pipelining scheduling for modern superscalar architectures. (I) We explore ways to improve compile time performance by producing more accurate lower bounds for II\sb{min}. Our new scheme accounts for register use and lets the scheduler provide guidance to the allocator. The scheduling process of the loops that benefited from this technique was 18% to 30% faster. (II) We explore new techniques for improving the schedules of loops that contain complex control flow. Our proposed techniques do not require the addition of specialized hardware. The initiation intervals for those loops were reduced by 25% to 36%
Cluster assignment and instruction scheduling for partitioned register-set machines
No full textFor half a century, computer architects have been striving to improve uniprocessor computer performance. Many of their successful designs such as VLIW and superscalar machines use multiple functional units trying to exploit instruction level parallelism in computer programs. As the number of functional units rises, another hardware constraint enters the picture---the number of register-file ports needed grows directly with the number of functional units. At some point, the multiplexing logic on register ports can come to dominate the processor's cycle time. A reasonable solution is to partition the register file into independent sets and associate each functional unit with a specific register set. Such partitioned register sets have appeared in a number of commercial machines, such as Texas Instruments TMS320C6xxx DSP chips.
Partitioned register-set architectures present a new set of challenges to compiler designers---the compiler must assign each operation to a specific clusters and coordinate data movement between clusters. In this thesis, we investigate five instruction scheduling methods with different scopes to find a suitable one for partitioned register-set architectures. Next, we examine previous algorithms for the combined cluster assignment and scheduling problem and propose two new algorithms that improve upon the prior art. Then we study the difficulties introduced by limited number of registers and provide an approach to handle them. Finally we take several other measurements of partitioned register-set architectures that may shed light on some of the architectural decisions
N-variant Hardware Design
No full textThe emergence of lightweight embedded devices imposes stringent constraints on
the area and power of the circuits used to construct them. Meanwhile, many of
these embedded devices are used in applications that require diversity and flexibility
to make them secure and adaptable to the fluctuating workload or variable fabric.
While field programmable gate arrays (FPGAs) provide high flexibility, the use of
application specific integrated circuits (ASICs) to implement such devices is more
appealing because ASICs can currently provide an order of magnitude less area and
better performance in terms of power and speed. My proposed research introduces the
N-variant hardware design methodology that adds the sufficient flexibility needed by
such devices while preserving the performance and area advantages of using ASICs.
The N-variant hardware design embeds different variants of the design control
part on the same IC to provide diversity and flexibility. Because the control circuitry
usually represents a small fraction of the whole circuit, using multiple versions of the
control circuitry is expected to have a low overhead. The objective of my thesis is to
formulate a method that provides the following advantages: (i) ease of integration in
the current ASIC design flow, (ii) minimal impact on the performance and area of the
ASIC design, and (iii) providing a wide range of applications for hardware security
and tuning the performance of chips either statically (e.g., post-silicon optimization)
or dynamically (at runtime). This is achieved by adding diversity at two orthogonal
levels: (i) state space diversity, and (ii) scheduling diversity. State space diversity
expands the state space of the controller. Using state space diversity, we introduce
an authentication mechanism and the first active hardware metering schemes. On the
other hand, scheduling diversity is achieved by embedding different control schedules
in the same design. The scheduling diversity can be spatial, temporal, or a hybrid
of both methods. Spatial diversity is achieved by implementing multiple control
schedules that use various parts of the chip at different rates. Temporal diversity
provides variants of the controller that can operate at unequal speeds. A hybrid of
both spatial and temporal diversities can also be implemented. Scheduling diversity
is used to add the flexibility to tune the performance of the chip. An application
of the thermal management of the chip is demonstrated using scheduling diversity.
Experimental results show that the proposed method is easy to integrate in the current
ASIC flow, has a wide range of applications, and incurs low overhead
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