1,721,058 research outputs found
General Strategies to Design Nanometer Flip-Flops in the Energy-Delay Space
No full textIn this paper, a general and complete design flow for nanometer flip-flops (FFs) is presented. The proposed design methodology permits to optimize FFs under constraints within the energy-delay space through extensive adoption of the Logical Effort method, which also allows for defining the bounds in the design space search. Transistor sizing is rigorously discussed by referring to cases that occur in practical designs. Appropriate metrics with clear physical meaning are proposed and various interesting properties are derived from circuit analysis. A well-defined design procedure is derived that can be easily automated with commercial CAD tools. In contrast to previous works, the impact of local interconnections is explicitly accounted for in the design loop, as is required in nanometer CMOS technologies. A case study is discussed in detail to exemplify the application of the proposed methodology. Extensive simulations for a typical FF in a 65-nm CMOS technology are presented to show the whole design procedure and validate the underlying assumptions
Flip-Flop Energy/Performance versus Clock Slope and Impact on the Clock Network Design
No full textIn this paper, the influence of the clock slope on the speed of various classes of flip-flops (FFs) and on the overall energy dissipation of both FFs and clock domain buffers is analyzed. Analysis shows that an optimum clock slope exists, which minimizes the energy spent in a clock domain. Results show that the clock slope requirement can be relaxed with respect to traditional assumptions, leading up to 30-40% energy savings and at a very small speed performance penalty. The effectiveness of the clock slope optimization is discussed in detail for the existing classes of FFs. The impact of such an optimization in terms of additive skew and jitter contributions is discussed, together to the analysis of the impact of technology scaling. Extensive post-layout simulations on a 65-nm CMOS technology are performed to check the validity of the underlying assumptions and approximations
Variations in nanometer CMOS flip-flops: Part i - Impact of process variations on timing
No full textIn this paper, split into Part I and II, the impact of variations on single-edge triggered flip-flops (FFs) is comparatively evaluated across a wide range of state-of-the-art topologies. The analysis explicitly considers fundamental sources of variations such as process/voltage/temperature (PVT), as well as the clock network (clock slope variations). For each topology, the variations of performance, robustness against hold violations, energy and leakage are statistically evaluated and compared. The impact of layout parasitics is explicitly included in the circuit design loop. The presented results provide well-defined guidelines for variation-aware selection of the flip-flop topologies, and estimates for early budgeting of variations before detailed circuit design. Also, the analysis enables a deeper understanding of the sensitivity to variations of existing topologies across a wide range of sizes and loads. In particular, this Part I introduces the methodology, the targeted flip-flop topologies and investigates the impact of process variations on flip-flop timing
Optimum Clock Slope for Flip-Flops within a Clock Domain: Analysis and a Case Study
No full textIn this paper. The impact of clock slope specification oy the energy consumption of a clock domain is analyzed. Results show that the clock slope requirement can be relaxed at the cost of a very small speed penalty and energy increase i. The flip-flops (FFs). O. The other hand, relaxin. The clock slope specification allows for downsizin. The local buffers drivin. The FFs that belong to the same clock domain. Froy the energy point of view, an optimum clock slope is found that leads to energy savings of 30 ÷ 40 % compared to the usually adopted clock slopes. The effectiveness oy the clock slope optimization, includin. The impact on local skew/jitter sources, is discussed for the typical case of Master-Slave FFs by resorting to simulations on a 65-nm CMOS technology. ©2009 IEEE
Consoli e consolati italiani dagli Stati preunitari al fascismo (1802-1945)
Full text linkIl volume raccoglie tredici contributi dedicati al ruolo svolto da consoli e consolati nella
costruzione dello Stato e della nazione nell’Italia tra Otto e Novecento. Prima dell’Unità, negli
anni della «diaspora italiana», comunità e sistemi consolari erano divisi tra sei Stati preunitari,
seppur in presenza di una «italianità» già viva e attiva. Una italianità che è possibile ritrovare
attraverso pratiche ben documentate nelle fonti consolari e, in particolare, nella speciale
interazione esistente tra i consoli e i rispettivi rappresentati. L’obiettivo è stato dunque
quello di esaminare l’evoluzione delle amministrazioni consolari italiane in quei decenni
strategici e così rivelare quale sia stato il contributo di quelle istituzioni, impegnate in un
processo di modernizzazione e di burocratizzazione, nella formazione del legame tra Stato e
amministrati. I saggi ne seguono l’evoluzione attraverso il susseguirsi degli avvenimenti, dal
dominio imperiale francese ai tentativi delle monarchie conservatrici di creare delle identità
regionali, dalle vicende del lungo Quarantotto – che trasformò i consoli sardi nei promotori
dell’unificazione delle Italie in una Italia – al momento della «transizione unitaria» e dell’età
liberale, fino al Ventennio e ai nuovi compiti della promozione di una «italianità fascista».
Un percorso che mette in luce fino a che punto i sistemi consolari delle Italie pre- e postunitarie,
finora quasi del tutto ignorati dalla storiografia, siano stati protagonisti nella genesi
dello Stato e della nazione, tanto più se analizzati attraverso la lente comparativa e il confronto
con altre realtà d’oltreconfine
Physical Design Aware Comparison of Flip-Flops for High-Speed Energy-Efficient VLSI Circuits
No full textIn this paper, an extensive comparison of flip-flop (FF) topologies for high-speed applications is carried out in a 65-nm CMOS technology. This work goes beyond previous analyses in that traditional rankings do not include layout parasitics, which strongly affect both speed and energy and lead to drastic changes in the optimum transistor sizing. For this reason, in this work layout parasitics are included in the circuit design loop by adopting a novel strategy. The obtained results show that the energy efficiency and the performance of FFs is mainly determined by the regularity of their topology and layout. Finally, the area-delay tradeoff is also analyzed for the first time
Going Beyond Counting First Authors in Author Co-citation Analysis
Full text linkThe present study examines one of the fundamental aspects of author co-citation analysis (ACA) - the way co-citation
counts are defined. Co-citation counting provides the data on which all subsequent statistical analyses and mappings
are based, and we compare ACA results based on two different types of co-citation counting - the traditional type that
only counts the first one among a cited work's authors on the one hand and a non-traditional type that takes into
account the first 5 authors of a cited work on the other hand. Results indicate that the picture produced through this non-traditional author co-citation counting contains more coherent author groups and is therefore considerably clearer. However, this picture represents fewer specialties in the research field being studied than that produced through the traditional first-author co-citation counting when the same number of top-ranked authors is selected and analyzed. Reasons for these effects are discussed
Variations on the Author
Full text link“Variations on the Author” discusses two of Eduardo Coutinho’s recent films (Um Dia na Vida, from 2010, and Últimas Conversas, posthumously released in 2015) and their contribution to the general question of documentary authorship. The director’s filmography is characterized by a consistent yet self-effacing form of authorial self-inscription: Coutinho often features as an interviewer that rather than express opinions propels discourses; an interviewer that is good at listening. This mode of self-inscription characterizes him as an author who is not expressive but who is nonetheless markedly present on the screen. In Um Dia na Vida, however, Coutinho is completely absent form the image, while Últimas Conversas, on the contrary, includes a confessional prologue that moves the director from the margins to the center of his films. This article examines the ways in which these works stand out in the filmography of a director who offers new insights into the notion of cinematic authorship
Appropriate Similarity Measures for Author Cocitation Analysis
Full text linkWe provide a number of new insights into the methodological discussion about author cocitation analysis. We first argue that the use of the Pearson correlation for measuring the similarity between authors’ cocitation profiles is not very satisfactory. We then discuss what kind of similarity measures may be used as an alternative to the Pearson correlation. We consider three similarity measures in particular. One is the well-known cosine. The other two similarity measures have not been used before in the bibliometric literature. Finally, we show by means of an example that our findings have a high practical relevance.information science;Pearson correlation;cosine;similarity measure;author cocitation analysis
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