1,354,647 research outputs found
Going Beyond Counting First Authors in Author Co-citation Analysis
No full textThe present study examines one of the fundamental aspects of author co-citation analysis (ACA) - the way co-citation
counts are defined. Co-citation counting provides the data on which all subsequent statistical analyses and mappings
are based, and we compare ACA results based on two different types of co-citation counting - the traditional type that
only counts the first one among a cited work's authors on the one hand and a non-traditional type that takes into
account the first 5 authors of a cited work on the other hand. Results indicate that the picture produced through this non-traditional author co-citation counting contains more coherent author groups and is therefore considerably clearer. However, this picture represents fewer specialties in the research field being studied than that produced through the traditional first-author co-citation counting when the same number of top-ranked authors is selected and analyzed. Reasons for these effects are discussed
Variations on the Author
No full text“Variations on the Author” discusses two of Eduardo Coutinho’s recent films (Um Dia na Vida, from 2010, and Últimas Conversas, posthumously released in 2015) and their contribution to the general question of documentary authorship. The director’s filmography is characterized by a consistent yet self-effacing form of authorial self-inscription: Coutinho often features as an interviewer that rather than express opinions propels discourses; an interviewer that is good at listening. This mode of self-inscription characterizes him as an author who is not expressive but who is nonetheless markedly present on the screen. In Um Dia na Vida, however, Coutinho is completely absent form the image, while Últimas Conversas, on the contrary, includes a confessional prologue that moves the director from the margins to the center of his films. This article examines the ways in which these works stand out in the filmography of a director who offers new insights into the notion of cinematic authorship
A Reconfigurable Switched Capacitor DC-DC Converter with 1.9-6.3-V Input Voltage Range and 85 Peak Efficiency in 28-nm CMOS
No full textA reconfigurable step-down switched capacitor dc-dc converter (SCC) capable of operating over a wide input voltage range from 1.9 to 6.3 V is presented in this letter. The converter can be reconfigured in five different topologies, obtaining five different voltage conversion ratios, with a minimum overhead in terms of extra switches and flying capacitors. Prototypes implemented in a 28-nm CMOS technology can deliver up to 0.45-W output power while regulating the output voltage to 0.9 V with a 85 peak efficiency
Appropriate Similarity Measures for Author Cocitation Analysis
No full textWe provide a number of new insights into the methodological discussion about author cocitation analysis. We first argue that the use of the Pearson correlation for measuring the similarity between authors’ cocitation profiles is not very satisfactory. We then discuss what kind of similarity measures may be used as an alternative to the Pearson correlation. We consider three similarity measures in particular. One is the well-known cosine. The other two similarity measures have not been used before in the bibliometric literature. Finally, we show by means of an example that our findings have a high practical relevance.information science;Pearson correlation;cosine;similarity measure;author cocitation analysis
A low-phase-noise digital bang-bang PLL with fast lock over a wide lock range
No full textDigital phase-locked loops (DPLLs) based on binary phase detectors (BPDs) avoid power-hungry high-resolution time/digital converters (TDCs) while demonstrating advantages in area, power consumption, and design complexity. The introduction of digital/time converters (DTCs) enables fractional-N resolution at high spectral purity [1]. The design of a bang-bang digital PLL for wireless standards has two main challenges: quantization noise must be kept below the tolerable spot phase noise and fast lock must be guaranteed even for wide frequency steps. However, the overload of the BPD causes bang-bang PLLs to fail lock or to exhibit extremely long transients. A similar issue appears in the design of sub-sampling PLLs. This problem is exacerbated when the bang-bang PLL is designed for low phase noise for the tight resolution required of the digitally controlled oscillator (DCO). Fast locking techniques are usually based on the use of lookup tables [2], finite state machine [3], or gear shifting techniques, mostly in the field of clock-and-data recovery circuits (CDR) where spot noise performance is less of a concern. High-performance bang-bang PLLs (or subsampling PLLs) also include a frequency-aid circuit running in background [4], but its settling performance is seldom discussed
Chirp Generators for Millimeter-Wave FMCW Radars
No full textThe vast number of radar applications generates the demand for highly-linear, low-noise, fast chirp generators implemented in nanoscale CMOS technologies. Off-the-shelf chirp synthesizers are realized in BiCMOS technologies and demonstrate excellent phase noise performances, though, at high cost and limited modulation speed. This chapter describes a new class of fast and reconfigurable chirp generators based on digital bang-bang phase-locked loops, suitable for integration in modern CMOS processes. After analyzing the impact of the chirp generator impairments on a frequency-modulated continuous-wave (FMCW) radar system, a novel pre-distortion scheme for the linearization of critical blocks is introduced to achieve at the same time low phase noise and fast linear chirps. The chirp generator fabricated in 65-nm CMOS technology demonstrates above-state-of-the-art performance: It is capable of generating chirps around 23-GHz with slopes up to 173 MHz/μs and idle times of less than 200 ns with no over or undershoot after an abrupt frequency step. The circuit consuming 19.7 mA exhibits a phase noise of -100 dBc/Hz at 1 MHz offset from the carrier and a worst case in-band fractional spur level below -58 dBc
PLL-Based Wideband Frequency Modulator: Two-Point Injection Versus Pre-Emphasis Technique
No full textThis paper analyzes and compares two popular methods to widen the modulation bandwidth of a phase-locked loop, i.e., the pre-emphasis and the two-point injection technique. The analysis reveals that both architectures have the same sensitivity to gain errors and nonlinearity in the loop, though, compared with the pre-emphasis, the two-point injection scheme features less sources of error and does not require a phase detector with wide range and tight linearity requirements. The verification of the analysis as well as the comparison of the two modulation techniques is carried out on an accurate time-domain model of a 60-GHz digital phase-locked loop, taken as a case study and used to generate wideband chirp signals for a radar system
Analysis of millimeter-wave digital frequency modulators for ubiquitous sensors and radars
No full textThe need for low-noise, highly-linear, programmable chirp generators makes digital phase-locked loops (DPLLs) an attractive solution for radar sensors. This paper presents a general analysis and comparison of the two main techniques enabling wideband frequency modulation (FM) in PLLs, namely the two-point injection and the pre-emphasis. It is shown that while the two topologies are equivalent in term of mismatch error suppression, the required input range for the time-to-digital converter (TDC) is substantially lower in the two-point injection scheme, thus relaxing the TDC power consumption and linearity
A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter
No full textLocal oscillators for 5G wireless transceivers require rms integrated jitter below 100fs to enable spectrally efficient modulation schemes, such as high-order quadrature amplitude modulation (QAM), at millimeter-wave carrier frequencies. Analog PLLs demonstrated to have successfully met the required performance levels with integer-N [1] and fractional-N frequency synthesis [2], while involving large analog filters that are not amenable to down scaling in nanoscale CMOS processes. By contrast, digital PLLs are compact and scalable, but suffer from quantization noise of time-to-digital converters (TDCs), which adds up to thermal noise [3]. A viable solution to achieve both compactness and very low jitter is to employ an analog type-I PLL with a sampling phase detector (SPD) [4]. Unfortunately, the limited range of the SPD, combined with the tuning-dependent phase error, typical of a type-I PLL, which further reduces the available SPD range, produces a narrow PLL locking range and confines the architecture to integer-N frequency synthesis. This work presents a 12.5GHz fractional-N type-I sampling PLL achieving an rms jitter of 58.2fs (integrated from 1kHz to 100MHz) at 18mW power consumption and occupying an area of 0.16mm2. A 1b TDC with a simple digital phase-error-correction (DPEC) circuit is leveraged to simultaneously (i) limit the SPD phase error with no extra quantization noise and (ii) extract a digitized version of the phase error needed for the accurate cancellation of the fractional quantization error
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