1,721,109 research outputs found

    Efficient parallelization of Bowtie 2 with OpenCL on GPU

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    As a crucial and computation-intensive aspect in bioinformatics, sequence alignment has gained considerable attention from researchers and developers. Among all the sequence aligners, Bowtie 2 is one of the most commonly used, due to its high speed and accuracy. This thesis presents a parallel implementation of Bowtie 2 with OpenCL, which is a parallel programming model that is becoming widely known and receiving great interest from researchers in recent years. This OpenCL implementation has high portability on various devices, such as multi-core CPU, GPU, and FPGA. This thesis focuses on an efficient and accurate parallelization on GPU. Optimizations that can be accommodated to any devices have been applied, as well as GPU-related optimizations.Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2018-08-01The student, Yan Yan, accepted the attached license on 2016-07-21 at 01:03.The student, Yan Yan, submitted this Thesis for approval on 2016-07-21 at 01:04.This Thesis was approved for publication on 2016-07-21 at 09:05.DSpace SAF Submission Ingestion Package generated from Vireo submission #10048 on 2016-11-10 at 12:27:37Made available in DSpace on 2016-11-10T18:35:35Z (GMT). No. of bitstreams: 2 YAN-THESIS-2016.pdf: 1388134 bytes, checksum: 28b82fe5cbc5b927351dc3233f9b93e4 (MD5) LICENSE.txt: 4204 bytes, checksum: 279bbc545aefef5ae85ddbc588af1b5a (MD5) Previous issue date: 2016-07-21Embargo set by: Seth Robbins for item 95397 Lift date: 2018-11-10T18:35:44Z Reason: Author requested U of Illinois access only (OA after 2yrs) in Vireo ETD systemEmbargo set by: Seth Robbins for item 95397 Lift date: 2018-11-10T18:37:47Z Reason: Author requested U of Illinois access only (OA after 2yrs) in Vireo ETD systemEmbargo set by: Seth Robbins for item 95397 Lift date: 2018-11-10T18:39:22Z Reason: Author requested U of Illinois access only (OA after 2yrs) in Vireo ETD systemEmbargo set by: Seth Robbins for item 95397 Lift date: 2018-11-10T18:43:22Z Reason: Author requested U of Illinois access only (OA after 2yrs) in Vireo ETD systemU of I Only Restriction Lifted for Item 95397 on 2018-11-11T10:15:36Z

    GPU acceleration of advanced K-mer counting for computational genomics

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    k-mer counting is a popular pre-processing step in many bioinformatic algorithms. KMC2 is one of the most popular tools for k-mer counting. In this work, we leverage the computational power of the GPU to accelerate KMC2. Our goal is to reduce the overall runtime of many genome analysis tasks that use k-mer counting as an essential step. We achieved 4.03x speedup using one GTX 1080 Ti with one CPU (Xeon E5-2603) thread and 5.88x speedup using one GPU with four CPU threads over KMC2 running on a single CPU thread. This speedup is significant because accelerating k-mer counting is challenging due to reasons like serialized portions of code and overhead of disk operations.Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2020-08-01The student, Huiren Li, accepted the attached license on 2018-05-14 at 19:09.The student, Huiren Li, submitted this Thesis for approval on 2018-05-14 at 19:13.This Thesis was approved for publication on 2018-05-15 at 09:42.DSpace SAF Submission Ingestion Package generated from Vireo submission #12571 on 2018-09-27 at 11:15:40Made available in DSpace on 2018-09-27T16:28:01Z (GMT). No. of bitstreams: 2 LI-THESIS-2018.pdf: 303460 bytes, checksum: b65c6cb30886988a436e4bde92422b80 (MD5) LICENSE.txt: 4206 bytes, checksum: 7cac7663a7c217c758442af8d5fa3399 (MD5) Previous issue date: 2018-05-15Embargo set by: Seth Robbins for item 107736 Lift date: 2020-09-27T16:28:07Z Reason: Author requested U of Illinois access only (OA after 2yrs) in Vireo ETD systemEmbargo set by: Seth Robbins for item 107736 Lift date: 2020-09-27T16:30:34Z Reason: Author requested U of Illinois access only (OA after 2yrs) in Vireo ETD systemEmbargo set by: Seth Robbins for item 107736 Lift date: 2020-09-27T16:31:43Z Reason: Author requested U of Illinois access only (OA after 2yrs) in Vireo ETD systemEmbargo set by: Seth Robbins for item 107736 Lift date: 2020-09-27T16:34:29Z Reason: Author requested U of Illinois access only (OA after 2yrs) in Vireo ETD systemU of I Only Restriction Lifted for Item 107736 on 2020-09-28T09:15:24Z

    Going Beyond Counting First Authors in Author Co-citation Analysis

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    The present study examines one of the fundamental aspects of author co-citation analysis (ACA) - the way co-citation counts are defined. Co-citation counting provides the data on which all subsequent statistical analyses and mappings are based, and we compare ACA results based on two different types of co-citation counting - the traditional type that only counts the first one among a cited work's authors on the one hand and a non-traditional type that takes into account the first 5 authors of a cited work on the other hand. Results indicate that the picture produced through this non-traditional author co-citation counting contains more coherent author groups and is therefore considerably clearer. However, this picture represents fewer specialties in the research field being studied than that produced through the traditional first-author co-citation counting when the same number of top-ranked authors is selected and analyzed. Reasons for these effects are discussed

    Semi-supervised universal yolov3-spp with GIoU loss for autonomous driving object detection under sunny and foggy weather

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    Object detection for autonomous driving has made a huge progress in recent years. However, detecting objects in foggy weather is still a challenging problem. In this thesis, we first propose a two-stage pipeline for foggy weather object detection. The two-stage pipeline removes fog from images using a Generative Adversarial Network (GAN) based model called DehazeGAN. Then, an object detection step using GIoU YOLOv3-SPP is performed on the defogged images. Following the two-stage method, we introduce a supervised universal model that deals with object detection in both sunny and foggy weather. The supervised universal model is built with a universal adapter that consists a “feature map”-based attention module and a weather-based attention module. The “feature map”-based attention module has a parallel of Squeeze-and-Excitation (SE) adapters, where each SE adapter extracts different features from each channel. The weather-based attention module looks at the input image and assigns weights to each SE adapter so that the universal adapter can describe the weather of the input image. To evaluate the performance of the supervised universal model, we established a new benchmark called CPR-A containing the following datasets: COCO, Pascal VOC, and annotated RESIDE-β. RESIDE-β only contains foggy images captured from the real world while COCO ad Pascal VOC are general object detection datasets that contain mostly clear images. We then take advantage of unannotated images in our dataset by proposing a semi-supervised universal object detection pipeline. The performance of this semi-supervised universal model is tested on CPR-U which is constructed by CPR-A and unannotated RESIDE-β. Experimentally, the trained two-stage pipeline outperforms GIoU YOLOv3-SPP by 0.17 mAP. The supervised universal model trained on CPR-A outperforms single weather/domain models (GIoU YOLOv3-SPP and the proposed two-stage model). Semi-supervised universal model further improves mAP accuracy from 0.633 to 0.654.Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2022-05-01The student, Zhijie Jin, accepted the attached license on 2020-05-14 at 10:46.The student, Zhijie Jin, submitted this Thesis for approval on 2020-05-14 at 10:53.This Thesis was approved for publication on 2020-05-14 at 11:53.DSpace SAF Submission Ingestion Package generated from Vireo submission #14916 on 2020-08-25 at 17:39:13Made available in DSpace on 2020-08-27T00:46:53Z (GMT). No. of bitstreams: 2 JIN-THESIS-2020.pdf: 857579 bytes, checksum: aa837eca0862bb41724872719a89d1d3 (MD5) LICENSE.txt: 4207 bytes, checksum: 2414dc2b68872cf0d6c73ad2de8e390d (MD5) Previous issue date: 2020-05-14Embargo set by: Seth Robbins for item 115849 Lift date: 2022-08-27T00:46:59Z Reason: Author requested closed access (OA after 2yrs) in Vireo ETD systemEmbargo set by: Seth Robbins for item 115849 Lift date: 2022-08-27T00:50:22Z Reason: Author requested closed access (OA after 2yrs) in Vireo ETD systemEmbargo set by: Seth Robbins for item 115849 Lift date: 2022-08-27T00:51:40Z Reason: Author requested closed access (OA after 2yrs) in Vireo ETD systemAuthor requested closed access (OA after 2yrs) in Vireo ETD systemLimite

    Resource and data optimization for hardware implementation of deep neural networks targeting FPGA-based edge devices

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    Targeting convolutional neural networks (CNNs), we adopt the high level synthesis (HLS) design methodology and explore various optimization and synthesis techniques to optimize design on an FPGA. Our motivation is to target embedded devices that operate as edge devices. Recently, as machine learning algorithms have become more practical, there have been much effort to implement them on devices that can be used in our daily lives. However, unlike server devices, edge devices are relatively small and thus have much more limited resources and performance. Therefore, control of resource usage and optimization play an important role when we want to implement machine learning algorithms on an edge device. The key idea explored in this thesis is backward pipeline scheduling which optimizes the pipeline between CNN layers. This optimization technique is especially useful to utilize the limited on-chip memory resource for classifying an image on an edge device. We have achieved latency of 175.7 μs for classifying one image in the MNIST data set using the LeNet and 653.5 μs for classifying one image in the Cifar-10 data set using the CifarNet. For the LeNet we were able to maintain high accuracy of 97.6% for the MNIST data set and 83.4% for the Cifar-10 data set. We achieved the best single-image latency, 5.2x faster for the LeNet and 1.95x faster for the CifarNet, compared with NVIDIA Jetson TX1.Submission published under a 24 month embargo labeled 'U of I Access', the embargo will last until 2020-05-01The student, Xinheng Liu, accepted the attached license on 2018-04-25 at 16:17.The student, Xinheng Liu, submitted this Thesis for approval on 2018-04-25 at 16:32.This Thesis was approved for publication on 2018-04-25 at 16:58.DSpace SAF Submission Ingestion Package generated from Vireo submission #12495 on 2018-08-31 at 17:21:32Made available in DSpace on 2018-09-04T20:36:55Z (GMT). No. of bitstreams: 2 LIU-THESIS-2018.pdf: 465564 bytes, checksum: ccd535e973d80355683d1fc3c84fdfaa (MD5) LICENSE.txt: 4208 bytes, checksum: 212ed2f4def6a3d45de6a15fda79959f (MD5) Previous issue date: 2018-04-25Embargo set by: Seth Robbins for item 107312 Lift date: 2020-09-04T20:37:00Z Reason: Author requested U of Illinois access only (OA after 2yrs) in Vireo ETD systemEmbargo set by: Seth Robbins for item 107312 Lift date: 2020-09-04T20:42:08Z Reason: Author requested U of Illinois access only (OA after 2yrs) in Vireo ETD systemU of I Only Restriction Lifted for Item 107312 on 2020-09-05T09:15:20Z

    Accelerating lattice scoring of automatic speech recognition through acoustic pre-pruning on GPU

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    This thesis introduces an acoustic pre-pruning algorithm that speeds up lattice scoring for GMM based ASR systems, and a constrained agglomerative clustering algorithm that makes it possible to maintain the advantage of the new algorithm in a GPU implementation. The implementation undergoes 2% to 6% degradation in PER while accelerating the runtime of lattice scoring by 45X to 60X over a traditional CPU implementation.Item withdrawn by Laura Spradlin ([email protected]) on 2014-12-09T17:13:49Z Item was in collections: University of Illinois Theses & Dissertations (ID: 1) No. of bitstreams: 2 He_Di.docx: 209312 bytes, checksum: b9c9f0815ff0dd4bcd62fbc7e2dfe745 (MD5) He_Di.pdf: 611140 bytes, checksum: 83ffe02efcf57fc6104f0fcd700f756f (MD5)Made available in DSpace on 2015-01-21T19:56:09Z (GMT). No. of bitstreams: 2 Di_He.pdf: 611155 bytes, checksum: f2d746c5590a05c6681910c207d596cd (MD5) He_Di.docx: 209473 bytes, checksum: f3aa2b7599e5e5d72f157c25d1dccfd7 (MD5)Embargo set by: Seth Robbins for item 73208 Lift date: 2017-01-21T19:56:18Z Reason: Author requested U of Illinois access only (OA after 2yrs) in Vireo ETD systemU of I Only Restriction Lifted for Item 73208 on 2017-01-22T10:15:25Z

    FPGA acceleration of short read alignment with high-level synthesis

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    With the introduction of next-generation sequencing (NGS) technologies, DNA sequencing is becoming an increasingly widespread process. When performed on human patients, it can allow for the prediction and prevention of diseases. An essential part of this bioinformatics pipeline is short read alignment}, which refers to aligning short fragments of DNA to the large and expansive reference genome. This can be a very time-consuming process with much room for improvement. This thesis improves on Bowtie 2, an aligner that is already very popular and high-performing. Through the use of OpenCL, it is possible to parallelize this application for both GPU and FPGA by using the same code. Several different levels of parallelism are implemented in order to achieve speedup on Bowtie 2.Submission published under a 24 month embargo labeled 'Closed Access', the embargo will last until 2019-05-01The student, Daniel Chen, accepted the attached license on 2017-04-27 at 12:47.The student, Daniel Chen, submitted this Thesis for approval on 2017-04-27 at 12:56.This Thesis was approved for publication on 2017-04-27 at 14:01.DSpace SAF Submission Ingestion Package generated from Vireo submission #11114 on 2017-08-10 at 14:32:46Made available in DSpace on 2017-08-10T19:52:26Z (GMT). No. of bitstreams: 2 CHEN-THESIS-2017.pdf: 1090883 bytes, checksum: 64f4558b554fc4db8118a8940eeee9a3 (MD5) LICENSE.txt: 4208 bytes, checksum: c70669c9d108a9620292aac2937a402c (MD5) Previous issue date: 2017-04-27Embargo set by: Colleen Fallaw for item 102694 Lift date: 2019-08-10T21:25:30Z Reason: Author requested closed access (OA after 2yrs) in Vireo ETD systemLimited Restriction Lifted for Item 102694 on 2019-08-11T09:15:21Z

    Variations on the Author

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    “Variations on the Author” discusses two of Eduardo Coutinho’s recent films (Um Dia na Vida, from 2010, and Últimas Conversas, posthumously released in 2015) and their contribution to the general question of documentary authorship. The director’s filmography is characterized by a consistent yet self-effacing form of authorial self-inscription: Coutinho often features as an interviewer that rather than express opinions propels discourses; an interviewer that is good at listening. This mode of self-inscription characterizes him as an author who is not expressive but who is nonetheless markedly present on the screen. In Um Dia na Vida, however, Coutinho is completely absent form the image, while Últimas Conversas, on the contrary, includes a confessional prologue that moves the director from the margins to the center of his films. This article examines the ways in which these works stand out in the filmography of a director who offers new insights into the notion of cinematic authorship

    The case for reconfigurable general purpose GPU computing

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    General purpose graphics processing unit (GPU) computing (GPGPU) has emerged as a new paradigm for programmers to exploit massive amounts of parallelism for relatively low costs. The abundance of GPUs in desktop and mobile computing platforms makes them ideal for accelerating tasks on multiple devices. However, despite the massively parallel architecture, GPUs are limited by the applications that run on them. The generic architecture of a GPU allows it to accelerate a large variety of applications, but none of these applications are capable of exploiting the complete performance capabilities of the GPU. This underutilization results in wastage of resources and power. In this work, we propose to introduce reconfiguration to the GPU architecture in the hopes of being able to tune its architecture to maximize performance for a given application or redistribute resources so as to reduce power consumption.Item withdrawn by Mark Zulauf ([email protected]) on 2014-12-11T14:31:05Z Item was in collections: University of Illinois Theses & Dissertations (ID: 1) No. of bitstreams: 1 Dhar_Ashutosh.pdf: 335169 bytes, checksum: 2337310aac958754ede3e93030cca2fc (MD5)Made available in DSpace on 2015-01-21T19:59:31Z (GMT). No. of bitstreams: 1 Ashutosh_Dhar.pdf: 335169 bytes, checksum: 2337310aac958754ede3e93030cca2fc (MD5)Embargo set by: Seth Robbins for item 73292 Lift date: 2017-01-21T19:59:39Z Reason: Author requested closed access (OA after 2yrs) in Vireo ETD systemLimited Restriction Lifted for Item 73292 on 2017-01-22T10:15:40Z
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