1,721,121 research outputs found
Risultati preliminari di una prova di concimazione nell'arancio «Washington navel»
No full textIn this paper are reported the results of 4-year research on the effects of differential N, P, K
treatments on young «Washington navel» orange trees.
The following treatments were compared:
A - Control;
B - Nitrogen fertilization at rate of 60 Kg/ha per year (N);
C - Nitrogen and phosphorus fertilization at rates, respectively, of 60 Kg/ha and 120 Kg/ha
per year (NP);
D - Nitrogen and potassium fertilization at rates, respectively, of 60 Kg/ha and 90 Kg/ha
per year (NK);
E - Nitrogen, phosphorus, and potassium fertilization at rates, respectively, of 60 kg/ha, 120 kg/ha,
and 90 Kg/ha per year (NPK).
The results evidenced that 4 year later the start of the research the different treatments did
not influence tree growth, while N and Mn content of the leaves was increased by NP and NPK
treatments.
No difference was found between N, NK, and NPK treatments on the average yield, that was
reduced in NP treatment and in the control trees.
As for as the fruit quality is concerned, a higher juice percentage was found in fruits from the
control trees, while total soluble solids were increased by treatments NP and NPK
Adaptive Latency Insensitive Protocols andElastic Circuits with Early Evaluation: A Comparative Analysis
Full text linkAbstractLatency Insensitive Protocols (LIP) and Elastic Circuits (EC) solve the same problem of rendering a design tolerant to additional latencies caused by wires or computational elements. They are performance-limited by a firing semantics that enforces coherency through a lazy evaluation rule: Computation is enabled if all inputs to a block are simultaneously available. Adaptive LIP's (ALIP) and EC with early evaluation (ECEE) increase the performance by relaxing the evaluation rule: Computation is enabled as soon as the subset of inputs needed at a given time is available. Their difference in terms of implementation and behavior in selected cases justifies the need for the comparative analysis reported in this paper. Results have been obtained through simple examples, a single representative case-study already used in the context of both LIP's and EC and through extensive simulations over a suite of benchmarks
On-Chip Transparent Wire Pipelining (invited paper)
Full text linkWire pipelining has been proposed as a viable mean to break the discrepancy between decreasing gate delays and increasing wire delays in deep-submicron technologies. Far from being a straightforwardly applicable technique, this methodology requires a number of design modifications in order to insert it seamlessly in the current design flow. In this paper we briefly survey the methods presented by other researchers in the field and then we thoroughly analyze the solutions we recently proposed, ranging from system-level wire pipelining to physical design aspects
A Reconfigurable Depth-Wise Convolution Module for Heterogeneously Quantized DNNs
Full text linkIn Deep Neural Networks (DNN), the depth-wise separable convolution has often replaced the standard 2D convolution having much fewer parameters and operations. Another common technique to squeeze DNNs is heterogeneous quantization, which uses a different bitwidth for each layer. In this context we propose for the first time a novel Reconfigurable Depth-wise convolution Module (RDM), which uses multipliers that can be reconfigured to support 1, 2 or 4 operations at the same time at increasingly lower precision of the operands. We leveraged High Level Synthesis to produce five RDM variants with different channels parallelism to cover a wide range of DNNs. The comparisons with a non-configurable Standard Depth-wise convolution module (SDM) on a CMOS FDSOI 28-nm technology show a significant latency reduction for a given silicon area for the low-precision configurations
Multi-objective Framework for Training and Hardware Co-optimization in FPGAs
Full text linkAlthough several works have recently addressed the problem of performance co-optimization for hardware and network training for Convolutional Neural Networks, most of them considered either a fixed network or a given hardware architecture. In this work, we propose a new framework for joint optimization of network architecture and hardware configurations based on Bayesian Optimization (BO) on top of High Level Synthesis. The multi-objective nature of this framework allows for the definition of various hardware and network performance goals as well as multiple constraints, and the multi-objective BO allows to easily obtain a set of Pareto points. We evaluate our methodology on a network optimized for an FPGA target and show that the Pareto set obtained by the proposed joint-optimization outperforms other methods based on a separate optimization or random search
Adaptive Latency Insensitive Protocols
Full text linkLatency-insensitive design copes with excessive delays typical of global wires in current and future IC technologies. It achieves its goal via encapsulation of synchronous logic blocks in wrappers that communicate through a latency-insensitive protocol (LIP) and pipelined interconnects. Previously proposed solutions suffer from an excessive performance penalty in terms of throughput or from a lack of generality. This article presents an adaptive LIP that outperforms previous static implementations, as demonstrated by two relevant cases — a microprocessor and an MPEG encoder — whose components we made insensitive to the latencies of their interconnections through a newly developed wrapper. We also present an informal exposition of the theoretical basis of adaptive LIPs, as well as implementation detail
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