1,721,050 research outputs found
Design of the Compact Processing Module for the ATLAS Tile Calorimeter
No full textThe LHC plans a series of upgrades towards a High Luminosity LHC (HL-LHC) to increase up to 5-7 times the current nominal instantaneous luminosity. The ATLAS experiment will accommodate the detector and data acquisition system to the HL-LHC requirements during the Long Shutdown 3 (2024-2026), where the on- and off-detector electronics of Tile Calorimeter (TileCal) will be completely replaced with a new readout electronics system with new interfaces to the full-digital ATLAS trigger system. In the HL-LHC era, the on-detector electronics will stream digitized data from the PMTs to 128 Compact Processing Modules (CPMs) operated in 32 ATCA carrier blades located in the counting rooms, requiring a total bandwidth of 40 Tbps to read out the entire detector. The CPMs will be the core of the off-detector electronics, being responsible for the high-speed communication with the on-detector electronics and ATLAS DAQ system, clock distribution, data acquisition, and core processing functionalities. Each CPM is equipped with 8 Samtec FireFly modules connected to a Xilinx Kintex UltraScale FPGA for data buffering, online digital processing and on-detector electronics control. A Xilinx Artix 7 FPGA performs slow control functionalities for the clocking circuitry, power monitoring, Ethernet configuration, and monitors the phase drifts of the distributed clock. This contribution presents the design of the first CPMs for the ATLAS Tile Calorimeter and its integration into the ATLAS TDAQ system. The results of the early performance testing with the on-detector electronics and ATLAS DAQ system are discussed, as well as the layout design and firmware architecture
Development of the Compact Processing Module for the ATLAS Tile Calorimeter Phase-II Upgrade
No full texthe LHC Phase II Upgrade of the ATLAS Tile Calorimeter (TileCal) implies a new readout and trigger architecture. The on-detector readout electronics will transmit detector data to 32 Tile PreProcessor (TilePPr) boards in the counting rooms at the LHC frequency, sending selected data to the ATLAS FELIX and interface with the trigger systems. Each TilePPr is composed of four Compact Processing Modules (CPM) with single-width AMC form factor and one full-size ATCA carrier with 4 slots. This contribution presents the design of the CPMs and first experiences, and reviews the results of the TilePPr prototype for the TileCal Demonstrator programme
The PreProcessors for the ATLAS Tile Calorimeter Phase II Upgrade
No full textThe Large Hadron Collider (LHC) has envisaged a series of upgrades towards a High Luminosity LHC (HL-LHC) delivering five times the LHC nominal instantaneous luminosity. The ATLAS Phase II upgrade will accommodate the detector and data acquisition system for the HL-LHC. In particular, the Tile Hadronic Calorimeter (TileCal) will replace completely on- and off-detector electronics using a new read-out architecture. The digitized detector data will be transferred for every beam crossing to the super Read Out Drivers (sRODs) located in off-detector counting rooms with a total data bandwidth of roughly 80 Tbps. The sROD implements increased pipelines memories and must provide pre-processed digital trigger information to Level 0/1 systems. The sROD module represents the link between the on-detector electronics and the overall ATLAS data acquisition system. It also implements the interface between the Detector Control System (DCS) and the on-detector electronics which is used to control and monitor the high voltage distribution system. The sROD is responsible of transmitting the commands to configure, control and monitor the on-detector read-out electronics. We present the TileCal sROD requirements and plans for the Phase II Upgrade of ATLAS as well as performance results of the first sROD prototype which has been built for the TileCal Demonstrator
Performance of the TilePPr demonstrator for the ATLAS Tile Calorimeter Phase II Upgrade
No full textThe Tile Calorimeter Pre-processor (TilePPr) demonstrator is a high performance double AMC board based on FPGA resources and QSFP modules. This board has been designed in the framework of the ATLAS Tile Calorimeter (TileCal) Demonstrator Project for the Phase II Upgrade as the first stage of the off-detector electronics. The TilePPr demonstrator has been conceived for receiving and processing the data coming from the on-detector electronics of the TileCal Demonstrator module, as well as for configuring it. Moreover, the TilePPr demonstrator handles the communication with the Detector Control System to monitor and control the on-detector electronics
Clock Distribution and Readout Architecture for the ATLAS Tile Calorimeter at the HL-LHC
No full textThe Tile Calorimeter (TileCal) is one detector of the ATLAS experiment at the Large Hadron Collider (LHC). TileCal is a sampling calorimeter made of steel plates and plastic scintillators which are readout using approximately 10,000 PhotoMultipliers Tubes (PMTs). In 2024, the LHC will undergo a series of upgrades towards a High Luminosity LHC (HL-LHC) to deliver up to 7.5 times the current nominal instantaneous luminosity. The ATLAS Tile Phase II Upgrade will accommodate detector and data acquisition system to the HL-LHC requirements. The detector electronics will be redesigned using a new clock distribution and readout architecture with a full-digital trigger system. After the Long Shutdown 3 (2024-2026), the on-detector electronics will transfer digitized data for every bunch crossing (~25 ns) to the Tile PreProcessors (TilePPr) in the counting rooms with a total data bandwidth of 40 Tbps. The TilePPrs will store the detector data in pipeline memories to cope with the new ATLAS DAQ architecture requirements, and will interface with the Front End Link eXchange (FELIX) system and the first trigger level. The TilePPr boards will distribute the sampling clock to the on-detector electronics for synchronization with the LHC clock with fixed and deterministic latency. The upgraded readout strategy was fully validated in a Demonstrator system using prototypes of the upgraded electronics in several test beam campaigns between 2015 and 2018. This contribution presents a detailed description of the new clock and readout architecture, and the status of the readout electronics for TileCal at the HL-LHC
The sROD module for the ATLAS Tile Calorimeter upgrade demonstrator
No full textThis work presents the first prototype of the super Read-Out Driver (sROD) demonstrator board for the Tile Calorimeter Demonstrator project. This project aims to test the new readout electronics architecture for the Phase 2 Upgrade of the ATLAS Tile Calorimeter, replacing the front-end electronics of one complete drawer with the new electronics during the Long Shutdown 1 (2013-2014), in order to evaluate its performance. The sROD demonstrator board will receive and process data from a complete module. Moreover the sROD demonstrator board will send preprocessed data to the present trigger system, and will transmit trigger control and timing information (TTC) and Detector Control System (DCS) commands to the front-end. A detailed description of the sROD board design, firmware and control and data acquisition software. We also will present the first results of this module during the commissioning of the upgraded TileCal module
Integration and Commissioning of the ATLAS Tile Demonstrator Module for Run 3
No full textThe Tile Calorimeter (TileCal) is the central hadronic calorimeter of the ATLAS experiment at Large Hadron Collider (LHC). The LHC will undergo a series of upgrades leading into the High Luminosity LHC (HL-LHC). The TileCal Phase-II Upgrade will accommodate the detector readout electronics to the HL-LHC conditions using a new clock and readout strategy. The TileCal Phase-II upgrade project has undertaken an extensive R&D program. A Demonstrator module containing the upgraded on-detector readout electronics was built in 2014, evaluated during seven test beam campaigns, and inserted into the ATLAS experiment in 2019. This module will be operated in the ATLAS experiment during Run-3 (2022–2025) through a Tile PreProcessor (TilePPr) Demonstrator board implementing the upgraded clock and readout architecture envisioned for the HL-LHC. The TilePPr also provides backward compatibility of the Demonstrator module with the present ATLAS Trigger and Data AcQuisition and the Timing, Trigger and Command systems. During its commissioning, the performance of the upgrade electronics has been evaluated with calibration and cosmic runs, showing excellent performance in terms of low noise, signal quality, and timing. This paper describes the hardware and firmware for the implementation of the data acquisition system of the Demonstrator module and discusses the results of the integration tests performed during the commissioning of the Demonstrator module for Run 3
Integration and Commissioning of the ATLAS Tile Demonstrator Module for Run-3
No full textThe Tile Calorimeter (TileCal) is the central hadronic calorimeter of the ATLAS experiment at Large Hadron Collider (LHC). The LHC will undergo a series of upgrades leading into the High Luminosity LHC (HL-LHC). The TileCal Phase-II Upgrade will accommodate the detector readout electronics to the HL-LHC conditions using a new clock and readout strategy. The TileCal Phase-II upgrade project has undertaken an extensive R&D program. A Demonstrator module containing the upgraded on-detector readout electronics was built in 2014, evaluated during seven test beam campaigns, and inserted into the ATLAS experiment in 2019. This module will be operated in the ATLAS experiment during Run-3 (2022–2025) through a Tile PreProcessor (TilePPr) Demonstrator board implementing the upgraded clock and readout architecture envisioned for the HL-LHC. The TilePPr also provides backward compatibility of the Demonstrator module with the present ATLAS Trigger and Data AcQuisition and the Timing, Trigger and Command systems. This contribution describes in detail the hardware and firmware for the implementation of the data acquisition system of the Demonstrator module and discusses the results of the integration tests performed during the commissioning of the Demonstrator module for Run 3
Test Beam Studies for the upgrade of the ATLAS Tile Calorimeter read-out electronics for the HL-LHC
No full textThe High Luminosity Large Hadron Collider (HL-LHC) is expected to start in 2026 the delivery of 3-4/ab of proton-proton collisions with up to 200 collisions per proton bunch crossing. The electronics of the ATLAS Tile Calorimeter has to be upgraded to cope with longer latencies of up to 35 µs needed by the trigger system at such high pileup levels and higher read-out rates. The expected radiation doses will also exceed the qualification range of the current readout system. In 2016-2018, the beam from the the Super Proton Synchrotron (SPS) was used to test the read-out of the demonstator of the proposed digitizer/shaper and pre-processor cards. Modules of the Tile Calorimeter were irradiated with high energy pions, electrons, muons and kaons in the North Area of CERN and the signals were read-out by the demonstrator electronics. In additions,a test system based on Multi-anode photo-multipliers (MA-PMs) has been used to read-out the signals of the individual fibers on PMT bundles of the Tile Calorimeter. This presentation summarizes the setup for particle identification and study of the ATLAS Tile Calorimeter data taking in preparation for the production of main boards and digitizer/shaper boards for the photo-multiplier tubes and the results of the calibration and tests of the MA-PMs. The fully assembled and tested demonstrator of the upgrade electronics will be installed already in 2019, during the LHC long shutdown and will read-out a slice of the ATLAS Tile Calorimeter during Run 3. The pulse shape, uniformity, timing precision and read-out capability of the proposed electronics for the HL-LHC upgrade are demonstrated
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