1,721,025 research outputs found
neMEMSi: One step forward in wireless attitude and heading reference systems
No full textThis work presents neMEMSi, a novel MEMS based inertial and magnetic system-on-board with embedded processing and wireless communication capabilities, providing an ultra low-power and easy to use Attitude and Heading Reference System (AHRS). Main target applications are navigation systems and inertial based motion tracking technologies. The paper describes the architecture of neMEMSi and provides an evaluation of the performance in terms of key features of state-of-the-art AHRS
High accuracy injection circuit for the calibration of a large pixel sensor matrix
No full textSemiconductor pixel detectors, for particle tracking and vertexing in high energy physics experiments as well as for X-ray imaging, in particular for synchrotron light sources and XFELs, require a large area sensor matrix. This work will discuss the design and the characterization of a high-linearity, low dispersion injection circuit to be used for pixel-level calibration of detector readout electronics in a large pixel sensor matrix. The circuit provides a useful tool for the characterization of the readout electronics of the pixel cell unit for both monolithic active pixel sensors and hybrid pixel detectors. In the latter case, the circuit allows for precise analogue test of the readout channel already at the chip level, when no sensor is connected. Moreover, it provides a simple means for calibration of readout electronics once the detector has been connected to the chip. Two injection techniques can be provided by the circuit: one for a charge sensitive amplification and the other for a transresistance readout channel. The aim of the paper is to describe the architecture and the design guidelines of the calibration circuit, which has been implemented in a 130 nm CMOS technology. Moreover, experimental results of the proposed injection circuit will be presented in terms of linearity and dispersion
Development of a wireless low-power multi-sensor network for motion tracking applications
No full textThis work presents a novel wireless and low power Attitude and Heading Reference Systems network based on low-cost MEMS (Micro Electro-Mechanical System) sensors, developed for motion tracking systems. Biomedical and rehabilitation purposes as well as gaming and consumer electronics may be the potential applications of this network. The paper aims to describe the hardware architecture, the embedded sensor fusion algorithm and the motion tracking system
Pixel-Level charge and current injection circuit for high accuracy calibration of the DSSC Chip at the European XFEL
No full textThis work presents the experimental results from the characterization of the second prototype of a high accuracy (in terms of linearity, mismatch and noise) injection circuit to be used for in-pixel calibration of a large sensor matrix. The circuit was designed for the calibration of the pixel cell unit of a hybrid pixel device, the DEPFET Sensor with Signal Compression (DSSC) chip, for the large format imager at the European X-ray Free Electron Laser (XFEL), but, in principle, it can be used also for other kinds of detectors, e.g., deep N-well monolithic CMOS sensors. In the case of hybrid pixels, the injection circuit is particularly useful to test the functionality of the readout electronics already at the chip level, when no sensor is connected to the chip. Two injection techniques have been investigated: one for a charge sensitive amplification and the other for a transresistance readout channel. The aim of the paper is to describe the architecture of the calibration circuit, which has been implemented in a 130-nm CMOS technology, and to present the results from the characterization of the second prototype
Dynamic Compression of the Signal in a Charge Sensitive Amplifier: From Concept to Design
Full text linkThis work is concerned with the design of a low-noise Charge Sensitive Amplifier featuring a dynamic signal compression based on the non-linear features of an inversion-mode MOS capacitor. These features make the device suitable for applications where a non-linear characteristic of the front-end is required, such as in imaging instrumentation for free electron laser experiments. The aim of the paper is to discuss a methodology for the proper design of the feedback network enabling the dynamic signal compression. Starting from this compression solution, the design of a low-noise Charge Sensitive Amplifier is also discussed. The study has been carried out by referring to a 65 nm CMOS technology
Development of a Wearable In-Ear PPG System for Continuous Monitoring
No full textIn this paper, a wearable electronic platform for in-ear photoplethysmography is presented. The system
is specifically designed with a miniaturized form factor in order to enable the potential monitoring of athletes during physical activity, as well as professionals wearing earbuds or headphones during their normal duties. Measurements have been collected to address the main factors affecting the signal quality. As a result, the fine tuning of the configuration parameters allowed the extension of the battery lifetime of
the system to over 3 days of continuous operation. Moreover, an investigation of the best body measurement location has been carried out. Two different algorithms have been developed: the former is a lightweight procedure for heart rate (HR) estimation suitable for embedded implementation whereas the latter features a motion mitigation adaptive filter to compensate the effect of motion artifacts (MAs)
First operation of a DSSC hybrid 2D Soft X-ray imager with 4.5 MHz frame rate
No full textThe DSSC (DEPFET Sensor with Signal Compression) collaboration develops a hybrid pixelated X-Ray photon detector with 4.5 MHz frame rate and immediate amplitude digitization for experiments at the European XFEL. We present the first full format 14.9x14 mm^2 F1 pixel readout ASIC for the DSSC detector. The readout architecture is specially adapted to the burst structure of the XFEL (bursts of 2880 pulses spaced by down to 220 ns at a rate of 10 Hz) by in-pixel digitization and digital hit data storage and data transfer during the burst gaps. The readout ASIC contains 64x64 pixels of 229x204 um^2 size and includes per pixel two low noise front-end versions for DEPFET and silicon drift detectors (SDD), a single-slope 8-bit ADC and local memory. Measurements using the F1 ASIC and a matching mini-SDD sensor matrix are shown
Novel active signal compression in low-noise analog readout at future X-ray FEL facilities
No full textThis work presents the design of a low-noise front-end implementing a novel active signal compression technique. This feature can be exploited in the design of analog readout channels for application to the next generation free electron laser (FEL) experiments. The readout architecture includes the low-noise charge sensitive amplifier (CSA) with dynamic signal compression, a time variant shaper used to process the signal at the preamplifier output and a 10-bit successive approximation register (SAR) analog-to-digital converter (ADC). The channel will be operated in such a way to cope with the high frame rate (exceeding 1 MHz) foreseen for future XFEL machines. The choice of a 65 nm CMOS technology has been made in order to include all the building blocks in the target pixel pitch of 100 mu m. This work has been carried out in the frame of the PixFEL Project funded by the Istituto Nazionale di Fisica Nucleare (INFN), Italy
Low-noise fast charge sensitive amplifier with dynamic signal compression
No full textThis work is concerned with the experimental characterization of a Charge Sensitive Amplifier featuring dynamic signal compression, fast recovery time, low noise and reduced area occupancy. The device takes advantage of the non-linear features of an inversion-mode MOS capacitor to fit a wide input dynamic range into the available output swing. It can be operated in synchronous mode at high frame rates, of the order of few MHz, thanks to a wide bandwidth, an improved output stage and a fast reset network. The reduced area occupancy makes the amplifier suitable for integration in a 100x 100 μm2 pixel area. All these features make the device a good candidate for applications where a fast front-end with a non-linear response is required, such as in imaging instrumentation for Free Electron Laser experiments. The aim of the paper is to show the experimental results coming from the characterization of the first prototype of the circuit which has been designed in a 65 nm CMOS technology. within the PixFEL Project funded by the INFN, Italy
The DSSC Pixel Readout ASIC with Amplitude Digitization and Local Storage for DEPFET Sensor Matrices at the European XFEL
No full textThe DSSC (DEPFET Sensor with Signal Compression) consortium develops a 1MPixel detector for low energy X-rays at the European XFEL. The XFEL will produce 10 bursts per second, each containing 2880 X-ray pulses with a repetition rate of 4.5 MHz. X-ray photons of 0.5 − 6 keV are absorbed in hexagonal DEPFET pixels of 229x204 um^2 pitch with a nonlinear characteristic to achieve a high dynamic range. The sensors will be bump bonded to readout ASICs of 64x64 pixels. Each pixel contains a filter with trapezoidal weighting function, a single slope ADC of 8-9 Bit resolution and a digital memory to store 640 events. A veto mechanism allows to discard uninteresting events. The digital hit data is read out serially during the ≈ 100 ms long burst gaps. Prototype matrix chips of 8x8 pixels with the full functionality have been produced and characterized electronically and with DEPFET sensors. The architecture and the design of the 8x8 ASIC, measured results and an outlook to the large 64x64 pixel chip will be presented
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