1,721,150 research outputs found
A Write System for Compact RRAM Memory Arrays Based on F-1T1R
No full textThis paper presents a novel write system for memory array with RRAM devices. Our design targets the minimization of the write circuit area and a more compact memory array, by avoiding large-area IO transistors and exploiting the back-gate control in FD-SOI technologies. Indeed, thanks to the Flipped (F)-1T1R cell, replacing the standard 1T1R for the data storage, read and write peripheral circuits, on the columns, can be designed with core devices, to withstand the low reset voltage, for a reduced column pitch. Designed in a 22-nm FD-SOI technology, without IO devices, our write system can safely provide a forming voltage above 3 V and a reset voltage of 1.35 V, with very low values of leakage current. From the optimized layout, we obtained an area ratio, between the write system and the full memory, below 10%, for a memory array with 400 rows and columns
Ultra low-voltage analog circuits for UHF RFID devicesin 180 nm CMOS technology
Full text linkRadio-frequency identification by means of passive tags requires low-cost devices featuring extremely low power consumption for long reading distance and compatibility to small printed antennas. The paper describes the design and implementation of the key analog blocks in a RFID chip: power supply regulator, local oscillator and ASK demodulator. The proposed local oscillator exhibits a very low power consumption and achieves a frequency tolerance compatible with the requirements dictated by the ISO 18000-6 standards. In addition, an ultra-low power voltage reference and a regulator based on a zero-voltage threshold device are presented. These circuits are suitable to provide a regulated power supply to the local oscillator and to the core logic of the passive device. Measurements on a chip implemented in 0.18 μm digital CMOS technology validate the results obtained from simulations
Yield Enhancement by Multi-level Linear Modeling of Non-Idealities in an Interpolated Flash ADCA.
No full text
An Optimization Framework for Mixed-Signal Accelerators Based on F-2T2R Compute Cells
No full textThis paper proposes a Matlab framework for the optimized design of mixed-signal accelerator for Deep Neural Networks (DNNs), based on the Flipped (F)-2T2R RRAM compute cell. The manuscript describes an analytical model including the fundamental sources of accelerator non-ideality, developed for a simplified yet accurate system description. The framework allows to explore the design space and optimize the accelerator, targeting system level performance. A trade-off between the accelerator energy consumption and the maximum SNR emerges from simulations
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