1,720,963 research outputs found
Design techniques for secure cryptographic circuits in deep submicron technologies
Full text linkOne of the main concerns of modern cryptographic devices is related to the possibility of stealing the secret information, which is processed or stored inside (e.g. personal data, PIN, passwords, payment details, ...). In the scientific community many efforts have been spent in the last decades, with the purpose to develop cryptographic algorithms, which are robust enough against any attempt to detect the cryptographic key of the algorithm itself. In the last years a new class of attacks, aimed at attacking one device at the physical level, gained even more importance. Their efficacy consists in the possibility to exploit the physical emissions of the device (e.g. power consumption, light, noise, electromagnetic radiation, ...), instead that trying to break the algorithm from a mathematical point of view. This class of attacks is known as Side Channel Attacks (SCAs) and their danger resides in the fact that they allow to steal the information leaking from the device, without leaving any trace of their activity, so that the victim of the attack (e.g. the owner of a smart card) could be completely unaware of them. Many countermeasures have been presented at each design level, in order to protect electronic circuits, which are the hardware basis of any cryptographic device, against them. In this work we focus on a particular class of SCAs: Power Analysis Attacks (PAAs). PAAs are able to find correlation between the power consumption of a digital circuit and the electrically internally processed data, exploiting the fact that with the reduction of the dimensions of the commercial electronic technologies this dependance becomes even more relevant. Therefore the new challenge of the semiconductor companies is to design and manufacture devices which are proven against this class of attacks, already from a hardware point of view, in order to provide the customer with reliable and optimized products.
The main contributions of this work are below summarized:
Present a new concept for the design of digital cryptographic circuits, whose purpose is to increase the level of securiy of crypto-devices against hardware attacks, in particulat against PAAs.
- Discuss the most known state-of-the-art security metrics and present a new methodology, as an improvement of the former ones, which should be considered in order to properly validate sub-micron cryptographic circuits.
- Design a new digital standard cell library, using a commercial sub-micron technology node, which has been characterized with extensive simulations using commercial EDA tools and has been evaluated using the most common security metrics.
- Define a new design flow, using the proposed standard cell library, which has been adopted for the design of a cryptographic test-chip; the design phases and the security evaluation of the test-chip are widely described and allow to prove the level of robustness of the new design style.
- Discuss a new class of Power Analysis Attacks, based on the leakage coming from the static power, which is becoming predominant in scaled sub-micron technologies, and prove through extensive simulations that the most known countermeasures against PAAs are not robust enough and therefore new metrics and design styles would be necessary
Security evaluation and optimization of the delay-based dual-rail pre-charge logic in presence of early evaluation of data
No full textDelay-based Dual-rail Pre-charge Logic (DDPL) has been introduced for counteracting power analysis attacks. Basically DDPL allows to achieve a constant power consumption for each data transition even in presence of capacitive load mismatches, thanks to an asynchronous two-phases evaluation. Unlikely other secure logic styles, in DDPL the clock frequency does not fix the security level since it depends on the value of the delay Δ between the complementary signals, which can be designed to be lower than 1ns using current CMOS technologies. However no works exist in which the DPA-resistance of DDPL is tested in presence of early evaluation, due to the different arrival times of the signals. The aim of this work is to provide and validate through transistor level simulations a theoretical model of the variations of the delay Δ during the evaluation phase for each possible data configuration in order to assess the effect of the early evaluation in DDPL, and to design early evaluation free DDPL gates. Moreover a case study crypto-core implemented both with basic and optimized DDPL gates has been designed in which a Correlation Frequency Power Analysis (CFPA) attack is mounted so to detect any leakage on simulated current traces
A flip-flop implementation for the DPA-resistant Delay-based Dual-rail Pre-charge Logic family
No full textDelay-based Dual-rail Pre-charge Logic (DDPL) is a logic style introduced with the aim of hiding power consumption in cryptographic circuits when a Power Analysis (PA) attack is mounted. Its particular data encoding allows to make the adsorbed current constant for each data input combination, irrespective of capacitive load conditions. The purpose is breaking the link between dynamic power and data statistics and preventing power analysis. In this work we present a novel implementation of a dynamic differential master-slave flip-flop which is compatible with the DDPL data encoding. Efforts were made in order to design a fully dynamic master-slave architecture which does not require a conversion of the signals from dynamic to static domain. Moreover it will be shown that the area occupied is also reduced due to a compact differential layout. Simulations performed using a 65nm-CMOS process showed that the proposed circuit exhibits good performances in terms of average power and NED (Normalized Energy Deviation) as required in transistor level countermeasures against power analysis, and it outperforms other previously published DPA-resistant flip-flops in the real case of unbalanced load conditions. © 2013 Department of Microelectronics and Computer Science, Technical University of Lodz
Design and validation through a frequency-based metric of a new countermeasure to protect nanometer ICs from side-channel attacks
No full textElectrical and capacitive mismatches are outstanding issues in modern submicron technologies, and must be considered already during the design steps. In this work, we propose a novel hardware countermeasure based on the combination of a circuit- and a system-level methodology, which helps to reduce the data dependence of the instantaneous power consumption of cryptographic circuits. Accordingly, we define a specific design methodology, which is based on a novel data encoding and on the insertion of an on-chip filter implemented through capacitances in the layout. The new countermeasure, called time-enclosed logic (TEL), is able to hide the data dependence in a very short time interval (in the order of 100 ps in modern submicron technologies), constraining the minimum amount of bandwidth required from the attack setup. As a second and parallel contribution, we present a novel design time metric for validating our design, named frequency energy deviation, which is based on the investigation of the deviation of the frequency patterns of the current traces. By simulating a basic cell template under unbalanced capacitive condition, we show that standard dual-rail precharge logics exhibit a resilient leakage already at lower frequencies, whereas in TEL circuits the data dependence is shifted toward high frequencies. As a case study, we designed a TEL-featured cryptographic circuit using a 65-nm technology node, without any assumption on the routing of the logic gates. Correlation power analysis attacks with a Gaussian model have been then mounted against the circuit. Simulation results show that the proposed countermeasure can help to mitigate the electrical mismatches occurring in submicron technologies, offering a promising perspective for the design of power analysis resistant circuits
Univariate power analysis attacks exploiting static dissipation of nanometer CMOS VLSI circuits for cryptographic applications
No full textIn this work we focus on Power Analysis Attacks (PAAs) which exploit the dependence of the static current of sub- 50nm CMOS integrated circuits on the internally processed data. Spice level simulations of static current as a function of the input state have been carried out to show that static power consumption of nanometer logic gates continues to exhibit a strong dependence on input vector even for sub-50nm circuits and that the coefficient of variation for a nand gate is strongly increasing with the scaling of CMOS technology. We demonstrate that it is possible to recover the secret key of a cryptographic core by exploiting this data dependence by means of different statistical distinguishers. For the first time in the literature we formulate the Attack Exploiting Static Power (AESP) as a univariate attack by using the mutual information approach to quantify the information that leaks through the static power side channel independently from the adopted leakage model. This analysis shows that countermeasures conceived to protect cryptographic hardware from attacks based on dynamic power consumption (e.g. WDDL, MDPL, SABL) still exhibit a leakage through the static power side channel. Finally, we show that the Time Enclosed Logic (TEL) concept does not leak information through the static power (even in the worst case scenario in which the attacker can stop the clock signal) and is suitable to be used as a countermeasure against both attacks explointig dynamic power and attacks exploiting static power
Leakage Power Analysis attacks against a bit slice implementation of the Serpent block cipher2014 Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems (MIXDES)
No full textIn this work the effectiveness of Leakage Power Analysis (LPA), a new class of side-channel attacks against cryptographic circuits, has been demonstrated on a case study. LPA attacks have been mounted against a bit slice implementation of the Serpent block cipher. After having measured the leakage contribution of a bit slice unit inside the processor, chosen as selection function for LPA attacks, an adequate power model has been identified. In order to consider the on-chip noise due to the static consumption of the other logics inside the processor, an estimation of the SNR has been provided according to the count of equivalent gates. The bit slice sub-block has been designed in a 65nm CMOS technology node for different logic styles, i.e. CMOS, WDDL, MDPL, and SABI.. Simulations show that for each logic implementation the correct key of the algorithm has been recovered with a maximum of 50.000 measurements, demonstrating that LPA attack can be successfully carried out against a wide range of logic styles, even if they efficiently thwart standard DPA and CPA attacks. Static power is expected to become greater in downscaled technologies, and thus LPA must be considered a serious threat for the security of cryptographic VLSI circuits
Going Beyond Counting First Authors in Author Co-citation Analysis
Full text linkThe present study examines one of the fundamental aspects of author co-citation analysis (ACA) - the way co-citation
counts are defined. Co-citation counting provides the data on which all subsequent statistical analyses and mappings
are based, and we compare ACA results based on two different types of co-citation counting - the traditional type that
only counts the first one among a cited work's authors on the one hand and a non-traditional type that takes into
account the first 5 authors of a cited work on the other hand. Results indicate that the picture produced through this non-traditional author co-citation counting contains more coherent author groups and is therefore considerably clearer. However, this picture represents fewer specialties in the research field being studied than that produced through the traditional first-author co-citation counting when the same number of top-ranked authors is selected and analyzed. Reasons for these effects are discussed
Variations on the Author
Full text link“Variations on the Author” discusses two of Eduardo Coutinho’s recent films (Um Dia na Vida, from 2010, and Últimas Conversas, posthumously released in 2015) and their contribution to the general question of documentary authorship. The director’s filmography is characterized by a consistent yet self-effacing form of authorial self-inscription: Coutinho often features as an interviewer that rather than express opinions propels discourses; an interviewer that is good at listening. This mode of self-inscription characterizes him as an author who is not expressive but who is nonetheless markedly present on the screen. In Um Dia na Vida, however, Coutinho is completely absent form the image, while Últimas Conversas, on the contrary, includes a confessional prologue that moves the director from the margins to the center of his films. This article examines the ways in which these works stand out in the filmography of a director who offers new insights into the notion of cinematic authorship
Effectiveness of Leakage Power Analysis Attacks on DPA-Resistant Logic Styles Under Process Variations
No full textThis paper extends the analysis of the effectiveness of Leakage Power Analysis (LPA) attacks to cryptographic VLSI circuits on which circuit level countermeasures against Differential Power Analysis (DPA) are adopted. Security metrics used for assessing the DPA-resistance of crypto core implementations, such as the minimum number to disclosure (MTD) and the asymptotic correlation coefficient, have been extended to the case of LPA. The LPA-resistance has been evaluated in terms of MTD as a function of the on chip noise. Noise variances up to 10000 times greater than the signal variance have been taken into account and LPA attacks have been successfully executed for all the logic styles under analysis using less than 100000 measurements. Moreover the role of process variations has been investigated through extensive Monte Carlo simulations in order to evaluate their impact on the leakage model for the logic styles under analysis. Results show that LPA attacks can be successfully carried out on the different anti-DPA logic styles even in presence of process variations. To the best of our knowledge, this work proves for the first time the effectiveness of LPA attacks in a real scenario where on chip noise and process variations are taken into account
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