1,720,956 research outputs found
Going Beyond Counting First Authors in Author Co-citation Analysis
Full text linkThe present study examines one of the fundamental aspects of author co-citation analysis (ACA) - the way co-citation
counts are defined. Co-citation counting provides the data on which all subsequent statistical analyses and mappings
are based, and we compare ACA results based on two different types of co-citation counting - the traditional type that
only counts the first one among a cited work's authors on the one hand and a non-traditional type that takes into
account the first 5 authors of a cited work on the other hand. Results indicate that the picture produced through this non-traditional author co-citation counting contains more coherent author groups and is therefore considerably clearer. However, this picture represents fewer specialties in the research field being studied than that produced through the traditional first-author co-citation counting when the same number of top-ranked authors is selected and analyzed. Reasons for these effects are discussed
Variations on the Author
Full text link“Variations on the Author” discusses two of Eduardo Coutinho’s recent films (Um Dia na Vida, from 2010, and Últimas Conversas, posthumously released in 2015) and their contribution to the general question of documentary authorship. The director’s filmography is characterized by a consistent yet self-effacing form of authorial self-inscription: Coutinho often features as an interviewer that rather than express opinions propels discourses; an interviewer that is good at listening. This mode of self-inscription characterizes him as an author who is not expressive but who is nonetheless markedly present on the screen. In Um Dia na Vida, however, Coutinho is completely absent form the image, while Últimas Conversas, on the contrary, includes a confessional prologue that moves the director from the margins to the center of his films. This article examines the ways in which these works stand out in the filmography of a director who offers new insights into the notion of cinematic authorship
Appropriate Similarity Measures for Author Cocitation Analysis
Full text linkWe provide a number of new insights into the methodological discussion about author cocitation analysis. We first argue that the use of the Pearson correlation for measuring the similarity between authors’ cocitation profiles is not very satisfactory. We then discuss what kind of similarity measures may be used as an alternative to the Pearson correlation. We consider three similarity measures in particular. One is the well-known cosine. The other two similarity measures have not been used before in the bibliometric literature. Finally, we show by means of an example that our findings have a high practical relevance.information science;Pearson correlation;cosine;similarity measure;author cocitation analysis
Analyse et Modélisation de Réseaux d'Interconnexion Cohérent Puce-à-Puce
No full textThe slowdown of Moore’s Law has led to a paradigm shift in High-Performance Computing (HPC). As transistor density increases in silicon chips have decelerated, computer architects are forced to explore alternative approaches. This shift has given rise to chiplet-based System-on-Chip (SoC) architectures, where logic is distributed across multiple dies within a single package, instead of traditional monolithic single-chip multicore architectures. While this transition offers improved cost-efficiency and yields, it also introduces new challenges in design, evaluation, and optimization. Chiplet-based designs present both challenges and opportunities. They introduce varying intercore latencies but also enable post-tape-out heterogeneous integration, high-bandwidth on-package interconnects, and cache coherence across multiple interconnected chips. New protocols such as CCIX, UCIe, and OpenCAPI have emerged to facilitate communication between interconnected chips and maintain coherence. This approach allows for flexibility, ranging from single-chiplet CPUs for edge applications to multi-chiplet CPUs for high-performance cloud computing, all operating under asingle OS environment.Maintaining the coherence in modern multicore systems is already a challenging task. New protocols must frequently be designed and even if a new protocol is not a radical departure from previous protocols, designing and validating it are tedious, bug-prone processes. The extension of cache coherence from traditional monolithic multicore systems to multiple chiplets using independent cache-coherence protocols significantly increases design complexity. To address these challenges without resorting to time-intensive RTL designs, simulations, or costly tape-outs, high-level simulation is essential. However, existing architecture simulators, designed for monolithic chips, often lack the flexibility, detailed modeling capabilities, and OS control at the node level required to accurately simulate modern coherent interconnect protocols.Moreover, simulators with such capabilities are frequently proprietary, slowing down academic research and obscuring simulation details. This thesis aims to explore the modeling of coherent interconnect protocols forchiplet-based systems, focusing on multicore cache coherence and chip-to-chip interconnect protocols. We address several key limitations in existing solutions. Current multi-chiplet simulations often use multiple parallel simulator instances interconnected by external network simulators, each running its own OS, which poorly represents the targeted architectures. Additionally, monolithic network-on-chip (NoC) models that have been extended to multi-chip architectures often fail to extend coherence across all chips. Furthermore, open-source simulation platforms are typically complex and not natively compatible with multiple single network-on-chip handling. To tackle these issues, this thesis makes several main contributions. First, we present a methodology for modeling and designing models in modern, open-source system-level simulators. We present gem5 and explain all the key aspects of the simulator, as well as debugging strategies and considerations.Secondly, we discuss the challenges of accurately modeling coherent chip-to-chip interconnects, including chip-to-chip link management, maintaining coherence across multiple chips, and inter-chip routing. These insights provide a foundation for understanding the complexities involved in simulating modern multi-chip architectures, independently of the targeted simulator. Lastly, we present an implementation of a chip-to-chip interconnect model in gem5. This solution extends the Arm CHI protocol to multiple chips while maintaining coherence, allowing full-system simulation of real-world applications while maintaining a single-chip programmer’s perspective. We provide solutions to various modeling challenges and a methodology for calibrating the simulated model with a real hardware platform.This thesis offers a comprehensive package that includes both the methodology for designing new simulation models and addressing development challenges, as well as a complete implementation of a coherent chip-to-chip interconnect model. Our contribution represents an important step towards enabling accurate simulation of cache-coherent multi-chip architectures and aims to inspire future work in optimizing such architectures. By providing open-source tools and methodologies, we hope to accelerate research in this critical area of computer architecture, enabling more efficient and powerful computing systems in the future.Le ralentissement de la loi de Moore a conduit à un changement de paradigme dans le calcul haute performance (HPC), forçant les architectes informatiques à explorer des alternatives. Ce changement a donné naissance aux architectures System-on-Chip (SoC) basées sur des chiplets, où la logique est distribuée sur plusieurs dies au sein d’un même package, remplaçant les architectures multicœurs monolithiques traditionnelles. Bien que cette transition améliore la rentabilité et les rendements, elle introduit de nouveaux défis en matière de conception, d’évaluation et d’optimisation. Les conceptions basées sur les chiplets présentent à la fois des défis et des opportunités, introduisant des latences variables entre les cœurs tout en permettant une intégration hétérogène post-tape-out et des interconnexions à haute bande passante.De nouveaux protocoles comme CCIX, UCIe et OpenCAPI ont émergé pour faciliter la communication entre les puces interconnectées. Cette approche permet une flexibilité allant des CPUs à chiplet unique pour les applications edge aux CPUs multi-chiplets pour le cloud computing haute performance. Le maintien de la cohérence dans les systèmes multicœurs modernes est un défi, nécessitant une conception et une validation fréquentes des protocoles. L’extension de la cohérence de cache à plusieurs chiplets augmente significativement la complexité de conception. Bien que la simulation puisse répondre à ces défis sans recourir à des conceptions RTL chronophages ou des tape-outs coûteux, les simulateurs d’architectureexistants manquent souvent de flexibilité et de capacités nécessaires pour les protocoles d’interconnexion cohérents modernes. De plus, les simulateurs capables sont souvent propriétaires, entravant la recherche académique. Cette thèse explore la modélisation des protocoles d’interconnexion cohérents pour les systèmes basés sur les chiplets. Nous abordons les principales limitations des solutions existantes : les simulations multi-chiplets actuelles utilisent souvent plusieurs instances parallèles de simulateur avec des environnements OS séparés, représentant mal les architectures ciblées. De plus, les modèles network-on-chip monolithiques étendus échouent souvent à maintenir la cohérence entre les puces, et les plateformes open-source manquent généralement de support natif pour la gestion de multiple network-on-chip.Nos contributions incluent : premièrement, une méthodologie de modélisation dans les simulateurs système open-source modernes, présentant gem5 avec ses aspects clés et stratégies de débogage. Deuxièmement, une analyse des défis de la modélisation des interconnexions cohérentes puce à puce, fournissant des directives pour la simulation d’architectures multi-puces. Enfin, nous implémentons un modèle d’interconnexion puce à puce dans gem5, étendant le protocole Arm CHI à travers plusieurs puces tout en maintenant la cohérence et permettant une simulation full-system. Cette thèse fournit à la fois une méthodologie pour concevoir des modèles de simulation et une implémentation complète d’un modèle d’interconnexion cohérent puce à puce. Notre contribution fait progresser la simulation précise des architectures multi-puces cohérentes en cache et vise à inspirer de futurs travaux d’optimisation. Grâce aux outils et méthodologies open-source, nous cherchons à accélérer la recherche en architecture informatique, permettant des systèmes informatiques plus efficaces
Dispelling the Myths Behind First-author Citation Counts
Full text linkWe conducted a full-scale evaluative citation analysis study of scholars in the XML research field to explore just how different from each other author rankings resulting from different citation counting methods actually are, and to demonstrate the capability of emerging data and tools on the Web in supporting more realistic citation counting methods. Our results contest some common arguments for the continued
use of first-author citation counts in the evaluation of scholars, such as high correlations between author rankings by first-author citation counts and other citation
counting methods, and high costs of using more realistic citation counting methods that are not well-supported by the ISI databases. It is argued that increasingly available digital full text research papers make it possible for citation analysis studies to go beyond what the ISI databases have directly supported and to employ more
sophisticated methods
Analyse et Modélisation de Réseaux d'Interconnexion Cohérent Puce-à-Puce
No full textThe slowdown of Moore’s Law has led to a paradigm shift in High-Performance Computing (HPC). As transistor density increases in silicon chips have decelerated, computer architects are forced to explore alternative approaches. This shift has given rise to chiplet-based System-on-Chip (SoC) architectures, where logic is distributed across multiple dies within a single package, instead of traditional monolithic single-chip multicore architectures. While this transition offers improved cost-efficiency and yields, it also introduces new challenges in design, evaluation, and optimization. Chiplet-based designs present both challenges and opportunities. They introduce varying intercore latencies but also enable post-tape-out heterogeneous integration, high-bandwidth on-package interconnects, and cache coherence across multiple interconnected chips. New protocols such as CCIX, UCIe, and OpenCAPI have emerged to facilitate communication between interconnected chips and maintain coherence. This approach allows for flexibility, ranging from single-chiplet CPUs for edge applications to multi-chiplet CPUs for high-performance cloud computing, all operating under asingle OS environment.Maintaining the coherence in modern multicore systems is already a challenging task. New protocols must frequently be designed and even if a new protocol is not a radical departure from previous protocols, designing and validating it are tedious, bug-prone processes. The extension of cache coherence from traditional monolithic multicore systems to multiple chiplets using independent cache-coherence protocols significantly increases design complexity. To address these challenges without resorting to time-intensive RTL designs, simulations, or costly tape-outs, high-level simulation is essential. However, existing architecture simulators, designed for monolithic chips, often lack the flexibility, detailed modeling capabilities, and OS control at the node level required to accurately simulate modern coherent interconnect protocols.Moreover, simulators with such capabilities are frequently proprietary, slowing down academic research and obscuring simulation details. This thesis aims to explore the modeling of coherent interconnect protocols forchiplet-based systems, focusing on multicore cache coherence and chip-to-chip interconnect protocols. We address several key limitations in existing solutions. Current multi-chiplet simulations often use multiple parallel simulator instances interconnected by external network simulators, each running its own OS, which poorly represents the targeted architectures. Additionally, monolithic network-on-chip (NoC) models that have been extended to multi-chip architectures often fail to extend coherence across all chips. Furthermore, open-source simulation platforms are typically complex and not natively compatible with multiple single network-on-chip handling. To tackle these issues, this thesis makes several main contributions. First, we present a methodology for modeling and designing models in modern, open-source system-level simulators. We present gem5 and explain all the key aspects of the simulator, as well as debugging strategies and considerations.Secondly, we discuss the challenges of accurately modeling coherent chip-to-chip interconnects, including chip-to-chip link management, maintaining coherence across multiple chips, and inter-chip routing. These insights provide a foundation for understanding the complexities involved in simulating modern multi-chip architectures, independently of the targeted simulator. Lastly, we present an implementation of a chip-to-chip interconnect model in gem5. This solution extends the Arm CHI protocol to multiple chips while maintaining coherence, allowing full-system simulation of real-world applications while maintaining a single-chip programmer’s perspective. We provide solutions to various modeling challenges and a methodology for calibrating the simulated model with a real hardware platform.This thesis offers a comprehensive package that includes both the methodology for designing new simulation models and addressing development challenges, as well as a complete implementation of a coherent chip-to-chip interconnect model. Our contribution represents an important step towards enabling accurate simulation of cache-coherent multi-chip architectures and aims to inspire future work in optimizing such architectures. By providing open-source tools and methodologies, we hope to accelerate research in this critical area of computer architecture, enabling more efficient and powerful computing systems in the future.Le ralentissement de la loi de Moore a conduit à un changement de paradigme dans le calcul haute performance (HPC), forçant les architectes informatiques à explorer des alternatives. Ce changement a donné naissance aux architectures System-on-Chip (SoC) basées sur des chiplets, où la logique est distribuée sur plusieurs dies au sein d’un même package, remplaçant les architectures multicœurs monolithiques traditionnelles. Bien que cette transition améliore la rentabilité et les rendements, elle introduit de nouveaux défis en matière de conception, d’évaluation et d’optimisation. Les conceptions basées sur les chiplets présentent à la fois des défis et des opportunités, introduisant des latences variables entre les cœurs tout en permettant une intégration hétérogène post-tape-out et des interconnexions à haute bande passante.De nouveaux protocoles comme CCIX, UCIe et OpenCAPI ont émergé pour faciliter la communication entre les puces interconnectées. Cette approche permet une flexibilité allant des CPUs à chiplet unique pour les applications edge aux CPUs multi-chiplets pour le cloud computing haute performance. Le maintien de la cohérence dans les systèmes multicœurs modernes est un défi, nécessitant une conception et une validation fréquentes des protocoles. L’extension de la cohérence de cache à plusieurs chiplets augmente significativement la complexité de conception. Bien que la simulation puisse répondre à ces défis sans recourir à des conceptions RTL chronophages ou des tape-outs coûteux, les simulateurs d’architectureexistants manquent souvent de flexibilité et de capacités nécessaires pour les protocoles d’interconnexion cohérents modernes. De plus, les simulateurs capables sont souvent propriétaires, entravant la recherche académique. Cette thèse explore la modélisation des protocoles d’interconnexion cohérents pour les systèmes basés sur les chiplets. Nous abordons les principales limitations des solutions existantes : les simulations multi-chiplets actuelles utilisent souvent plusieurs instances parallèles de simulateur avec des environnements OS séparés, représentant mal les architectures ciblées. De plus, les modèles network-on-chip monolithiques étendus échouent souvent à maintenir la cohérence entre les puces, et les plateformes open-source manquent généralement de support natif pour la gestion de multiple network-on-chip.Nos contributions incluent : premièrement, une méthodologie de modélisation dans les simulateurs système open-source modernes, présentant gem5 avec ses aspects clés et stratégies de débogage. Deuxièmement, une analyse des défis de la modélisation des interconnexions cohérentes puce à puce, fournissant des directives pour la simulation d’architectures multi-puces. Enfin, nous implémentons un modèle d’interconnexion puce à puce dans gem5, étendant le protocole Arm CHI à travers plusieurs puces tout en maintenant la cohérence et permettant une simulation full-system. Cette thèse fournit à la fois une méthodologie pour concevoir des modèles de simulation et une implémentation complète d’un modèle d’interconnexion cohérent puce à puce. Notre contribution fait progresser la simulation précise des architectures multi-puces cohérentes en cache et vise à inspirer de futurs travaux d’optimisation. Grâce aux outils et méthodologies open-source, nous cherchons à accélérer la recherche en architecture informatique, permettant des systèmes informatiques plus efficaces
Analyse et Modélisation de Réseaux d'Interconnexion Cohérent Puce-à-Puce
No full textThe slowdown of Moore's Law has led to a paradigm shift in High-Performance Computing (HPC), forcing computer architects to explore alternatives. This shift has given rise to chiplet-based System-on-Chip (SoC) architectures, where logic is distributed across multiple dies within a single package, instead of traditional monolithic single-chip multicore architectures. While this transition improves cost-efficiency and yields, it introduces new challenges in design, evaluation, and optimization. Chiplet-based designs present both challenges and opportunities, introducing varying intercore latencies while enabling post-tape-out heterogeneous integration and high-bandwidth on-package interconnects. New protocols like CCIX, UCIe, and OpenCAPI have emerged to facilitate communication between interconnected chips. This approach allows flexibility from single-chiplet CPUs for edge applications to multi-chiplet CPUs for high-performance cloud computing. Maintaining coherence in modern multicore systems is challenging, requiring frequent protocol design and validation. The extension of cache coherence to multiple chiplets significantly increases design complexity. While high-level simulation could address these challenges without time-intensive RTL designs or costly tape-outs, existing architecture simulators often lack the flexibility and capabilities needed for modern coherent interconnect protocols. Moreover, capable simulators are frequently proprietary, hindering academic research. This thesis explores the modeling of coherent interconnect protocols for chiplet-based systems. We address key limitations in existing solutions: current multi-chiplet simulations often use multiple parallel simulator instances with separate OS environments, poorly representing targeted architectures. Additionally, extended monolithic network-on-chip models often fail to maintain coherence across chips, and open-source platforms typically lack native support for multiple network-on-chip handling. Our contributions include: First, a methodology for modeling in modern, open-source system-level simulators, presenting gem5 with key aspects and debugging strategies. Second, an analysis of challenges in modeling coherent chip-to-chip interconnects, providing insights for simulating multi-chip architectures. Finally, we implement a chip-to-chip interconnect model in gem5, extending the Arm CHI protocol across multiple chips while maintaining coherence and enabling full-system simulation. This thesis provides both methodology for designing simulation models and a complete implementation of a coherent chip-to-chip interconnect model. Our contribution advances the accurate simulation of cache-coherent multi-chip architectures and aims to inspire future optimization work. Through open-source tools and methodologies, we seek to accelerate research in computer architecture, enabling more efficient computing systems.Le ralentissement de la loi de Moore a conduit à un changement de paradigme dans le calcul haute performance (HPC), forçant les architectes informatiques à explorer des alternatives. Ce changement a donné naissance aux architectures System-on-Chip (SoC) basées sur des chiplets, où la logique est distribuée sur plusieurs dies au sein d'un même package, remplaçant les architectures multicœurs monolithiques traditionnelles. Bien que cette transition améliore la rentabilité et les rendements, elle introduit de nouveaux défis en matière de conception, d'évaluation et d'optimisation. Les conceptions basées sur les chiplets présentent à la fois des défis et des opportunités, introduisant des latences variables entre les cœurs tout en permettant une intégration hétérogène post-tape-out et des interconnexions à haute bande passante. De nouveaux protocoles comme CCIX, UCIe et OpenCAPI ont émergé pour faciliter la communication entre les puces interconnectées. Cette approche permet une flexibilité allant des CPUs à chiplet unique pour les applications edge aux CPUs multi-chiplets pour le cloud computing haute performance. Le maintien de la cohérence dans les systèmes multicœurs modernes est un défi, nécessitant une conception et une validation fréquentes des protocoles. L'extension de la cohérence de cache à plusieurs chiplets augmente significativement la complexité de conception. Bien que la simulation puisse répondre à ces défis sans recourir à des conceptions RTL chronophages ou des tape-outs coûteux, les simulateurs d'architecture existants manquent souvent de flexibilité et de capacités nécessaires pour les protocoles d'interconnexion cohérents modernes. De plus, les simulateurs capables sont souvent propriétaires, entravant la recherche académique. Cette thèse explore la modélisation des protocoles d'interconnexion cohérents pour les systèmes basés sur les chiplets. Nous abordons les principales limitations des solutions existantes : les simulations multi-chiplets actuelles utilisent souvent plusieurs instances parallèles de simulateur avec des environnements OS séparés, représentant mal les architectures ciblées. De plus, les modèles network-on-chip monolithiques étendus échouent souvent à maintenir la cohérence entre les puces, et les plateformes open-source manquent généralement de support natif pour la gestion de multiple network-on-chip. Nos contributions incluent : premièrement, une méthodologie de modélisation dans les simulateurs système open-source modernes, présentant gem5 avec ses aspects clés et stratégies de débogage. Deuxièmement, une analyse des défis de la modélisation des interconnexions cohérentes puce à puce, fournissant des directives pour la simulation d'architectures multi-puces. Enfin, nous implémentons un modèle d'interconnexion puce à puce dans gem5, étendant le protocole Arm CHI à travers plusieurs puces tout en maintenant la cohérence et permettant une simulation full-system. Cette thèse fournit à la fois une méthodologie pour concevoir des modèles de simulation et une implémentation complète d'un modèle d'interconnexion cohérent puce à puce. Notre contribution fait progresser la simulation précise des architectures multi-puces cohérentes en cache et vise à inspirer de futurs travaux d'optimisation. Grâce aux outils et méthodologies open-source, nous cherchons à accélérer la recherche en architecture informatique, permettant des systèmes informatiques plus efficaces
koamabayili/VECTRON-author-checklist: VECTRON author checklist
No full textWe have done our best to complete the author checklist relating to the use of animals in the hut study. Note that the objective for the hut study was to evaluate the IRS treatment applications for residual efficacy against Anopheles mosquitoes, including the local An. coluzzii mosquito population. Cows were only used to attract mosquitoes into the huts and no tests were carried out directly on the cows. The author checklist is intended for use with studies where experiments are carried out on animals, which is why we have had such difficulty in completing this for the hut study, as many of the questions do not relate to how the cows were used
- …
