1,721,041 research outputs found
La voce del reale. Il rapporto voce-immagine nel cinema documentario
Full text linkLa tesi propone un’indagine sul rapporto tra il piano visivo e la voce fuori campo nel cinema documentario. A fronte di una ricostruzione teorica del ruolo della voce off nel cinema e di una genealogica delle trasformazioni del commento parlato in rapporto all’immagine documentaria nel corso della Storia, si dedicherà un approfondimento al documentario italiano contemporaneo come caso esemplificativo di una voce fuori campo capace di inserirsi nell’intreccio intermediale del racconto e di mantenere al contempo il suo tratto specifico di declamazione orale
Performance, Area and Power Breakdown Analysis for NoC switches in 65nm technology
No full textLeveraging a development effort of the synthesis backend for Networks-on-Chip (NoCs), this work
contributes an analysis of the performance, area and power/energy breakdown of NoC switches in 65nm
technology. In particular, an architecture-level technique (control- and data-path decoupling) is deployed
to derive switch implementation variants optimized for different design objectives, and is then
validated against placement-aware logic synthesis
Cross-Layer Hardware/Software Assessment of the Open-Source NVDLA Configurable Deep Learning Accelerator
No full textThe NVIDIA Deep Learning Accelerator (NVDLA) is a free and open architecture that aims at promoting a standard way of designing deep neural network (DNN) inference engines. The analogy between open-source software and hardware points to FPGAS as ideal implementation platforms for open hardware accelerators. However, the instantiation flexibility enabled by reconfigurable logic should be correlated to the capacity of cost-effective devices. This paper explores the resource utilization-performance trade-offs spanned by the main precompiled NVDLA accelerator configurations on top of the mainstream Zynq UltraScale+ MPSoC. For the sake of comprehensive end-to-end performance characterization, the inference rate of the software stack is matched to that of the accelerator hardware, thus identifying current bottlenecks and promising optimization directions
Synergistic use of multiple on-chip networks for ultra-low latency and scalable distributed routing reconfiguration
No full textExtending the principle of partially good die allowance to manycore processors, and testing them over time to detect the onset of permanent faults, are only feasible through proper support in the on-chip interconnection network. In fact, this implies the ability to reconfigure the routing algorithm at runtime to reflect changes in network topologies. Current literature cannot avoid a large hardware and/or software overhead when tackling this challenge. This paper exploits the existence of multiple physical networks in industry-relevant manycore processors in a synergistic way, for the sake of fast and scalable distributed reconfiguration of the routing function at runtime
An Asynchronous Soft Macro for Ultra-Low Power Communication in Neuromorphic Computing
No full textAsynchronous networks-on-chip (NoCs) playa fundamental role to materialize energy efficiency and scalability of spiking neural network-based neuromorphic systems. An unmistakable trend in this field consists of using bundled-data encoding for NoC design, showing promise in overall cost metrics while incorporating moderate timing constraints. To date, no framework exists for cost-effective and flexible NoC design with this approach. This paper aims at bridging this gap, by making bundled-data NoCs available to neuromorphic system designers through a highly-configurable and technology-independent soft macro. To our knowledge, this is the first paper to prove synchronous-equivalent design flexibility for an asynchronous NoC
Transparent lifetime built-in self-testing of networks-on-chip through the selective non-concurrent testing of their communication channels
No full textIn some application domains (e.g., mission-critical systems), proactive detection of reliability threats or prompt fault containment are mandatory in order to avoid or limit the malfunctioning of electronic systems as an effect of the onset of permanent faults at runtime. As an essential milestone for the design of these systems, this paper presents a distributed and lightweight control framework for the built-in self-testing of networks-on-chip (NoCs) in the background while applications are running. The main idea of this concurrent online testing framework consists of modularizing the NoC into communication channels, of selectively taking such channels offline for non-concurrent testing, and of reconfiguring the NoC routing function to route packets around the temporary blockages to preserve network availability
Network-on-chip architectures and design methods
No full textSystem-on-Chip (SoC) represents the next major market for microelectronics, and there is considerable interest world-wide in developing effective methods and tools to support the SoC paradigm. SoC is an expanding field, at present the technical and technological literature about the overall state-of-the-art in SoC is dispersed across a wide spectrum which includes books, journals, and conference proceedings. The book provides a comprehensive and accessible source of state-of-the-art information on existing and emerging SoC key research areas, provided by leading experts in the field. This book covers the general principles of designing, validating and testing complex embedded computing systems and their underlying tradeoffs. The book has twenty five chapters organised into eight parts, each part focuses on a particular topic of SoC. Each chapter has some background covering the basic principles, and extensive list of references. It is aimed at graduate students,! designers and managers working in Electronic and Computer engineering
Going Beyond Counting First Authors in Author Co-citation Analysis
Full text linkThe present study examines one of the fundamental aspects of author co-citation analysis (ACA) - the way co-citation
counts are defined. Co-citation counting provides the data on which all subsequent statistical analyses and mappings
are based, and we compare ACA results based on two different types of co-citation counting - the traditional type that
only counts the first one among a cited work's authors on the one hand and a non-traditional type that takes into
account the first 5 authors of a cited work on the other hand. Results indicate that the picture produced through this non-traditional author co-citation counting contains more coherent author groups and is therefore considerably clearer. However, this picture represents fewer specialties in the research field being studied than that produced through the traditional first-author co-citation counting when the same number of top-ranked authors is selected and analyzed. Reasons for these effects are discussed
Control- and Data-Path Decoupling in the Design of a NoC Switch: Area, Power and Performance
No full textNetworks on chip are emerging as a disruptive technology to tackle the problem of scalable on-chip communication. An intensive research effort is being devoted to customizing generic network building blocks for specific design objectives such as low-latency or low-power. In this work, we identify in control and datapath decoupling inside a switch architecture an effective means of achieving the needed flexibility, while taking into account the switching, buffering and flow control implications of each design point. We deploy a 65 nm low-power technology library to explore the performance-power trade-off in the design of a NoC switch with area awareness, while leveraging placement-aware logic synthesis tools to deal with the predictability challenges posed by nanoscale designs
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