104,790 research outputs found
Analysis of 4H-SiC MOSFET with distinct high-k/4H-SiC interfaces under high temperature and carrier-trapping conditions
No full textIn this work, the reliability of different oxide/4H-SiC interfaces under high temperature and carrier-trapping conditions are investigated carefully. In more detail, the carrier-trapping and temperature effects are considered in the electrical characterization of a low breakdown 4H-SiC-based MOSFET by using in turn SiO2, Si3N4, AlN, Al2O3, Y2O3 and HfO2 as gate dielectric. A gate oxide with a high relative permittivity notably improves the transistor performance. In addition, HfO2 assures the MOSFET best immunity behaviors. The obtained results are explained in terms of the carrier channel mobility, device on-state resistance, and oxide electric field. By using HfO2, however, an increased gate leakage current is calculated. This drawback is overcome by inserting a thin interfacial layer (2 nm-thick) in the HfO2/4H-SiC MOS structure. In particular, two alternative gate stacked dielectrics, involving either SiO2 or Al2O3, have proven their effectiveness in preserving the transistor on-state figures of merit while limiting the gate leakage current in the whole explored gate voltage range. To support the prediction capabilities of the presented modeling analysis, the simulations results are compared with experimental data from literature resulting in a good agreement. Low power MOSFETs are used in several applications for which reliability and durability are as critical as performance. For example, referring to power optimizers for photovoltaic (PV) modules, which fall under the low-load and low-voltage category of DC–DC converters, these devices significantly increase the energy generated by each single PV module operating under harsh conditions and stressing environments. In addition, they have to ensure high reliability over the long term of operation
Temperature and SiO2/4H-SiC interface trap effects on the electrical characteristics of low breakdown voltage MOSFETs
No full textThe temperature and carrier-trapping effects on the electrical characteristics of a 4H silicon carbide (4H-SiC) metal–oxide–semiconductor field effect transistor (MOSFET) dimensioned for a low breakdown voltage (BVDS) are investigated. Firstly, the impact of the temperature is evaluated referring to a fresh device (defects-free). In particular, the threshold voltage (Vth), channel mobility (μch), and on-state resistance (RON) are calculated in the temperature range of 300 K to 500 K starting from the device current–voltage characteristics. A defective MOSFET is then considered. A combined model of defect energy levels inside the 4H-SiC bandgap (deep and tail centers) and oxide-fixed traps is taken into account referring to literature data. The simulation results show that the SiO2/4H-SiC interface traps act to increase RON, reduce μch, and increase the sensitivity of Vth with temperature. In more detail, the deep-level traps in the mid-gap have a limited effect in determining RON once the tail traps contributions have been introduced. Also, for gate biases greater than about 2Vth (i.e., VGS > 12 V) the increase of mobile carriers in the inversion layer leads to an increased screening of traps which enhances the MOSFET output current limiting the RON increase in particular at low temperatures. Finally, a high oxide-fixed trap density meaningfully influences Vth (negative shifting) and penalizes the device drain current over the whole explored voltage range
Improving the efficiency of a-Si:H/c-Si thin heterojunction solar cells by using both antireflection coating engineering and diffraction grating
No full textIn this paper, we present an analytical study of the impact of light trapping and multilayer antireflection coating (ARC) on the electrical characteristics of n(a-Si:H)/i(a-Si:H)/p(c-Si)/p+(C-Si) heterojunction solar cells with intrinsic thin layer (SHJ). The developed analytical model considers a triangular texture morphology of the solar cell top surface and a double ARC layer. This model serves as a fitness function to optimize the device reliability against the interfacial traps using Grey Wolf optimization approach (GWO). The optimized solar cell reveals a high short circuit current I SC = 47.9 mA, an open circuit voltage V OC = 0.56 V, fill factor FF = 74.72% and a conversion efficiency improvement in the order of 30% over conventional planar solar cells efficiency. Not only the optimized SHJ solar cell exhibits higher performance in terms of figure of merits, but also shows superior interfacial traps reliability at the amorphous/crystalline interface. This reliability enhancement is due to a better surface texture control and intrinsic thin film layer tuning provided by GWO approach
Going Beyond Counting First Authors in Author Co-citation Analysis
Get PDFThe present study examines one of the fundamental aspects of author co-citation analysis (ACA) - the way co-citation
counts are defined. Co-citation counting provides the data on which all subsequent statistical analyses and mappings
are based, and we compare ACA results based on two different types of co-citation counting - the traditional type that
only counts the first one among a cited work's authors on the one hand and a non-traditional type that takes into
account the first 5 authors of a cited work on the other hand. Results indicate that the picture produced through this non-traditional author co-citation counting contains more coherent author groups and is therefore considerably clearer. However, this picture represents fewer specialties in the research field being studied than that produced through the traditional first-author co-citation counting when the same number of top-ranked authors is selected and analyzed. Reasons for these effects are discussed
Improved InxGa1_xP/GaAs /Ge tandem solar cell using light trapping engineering and multi-objective optimization approach
No full textIn this paper, an analytical model for studying the effect of light trapping mechanism on tandem solar cell performance is developed. The proposed model considers diffraction grating morphology and antireflection coating of the InxGa1_xP/GaAs/Ge tandem solar cell. The main photovoltaic figures of merit of the InxGa1_xP/GaAs/Ge tandem solar cell are investigated. The obtained results prove the outstanding capability of the light trapping mechanism to improve device performance. An efficiency of 32.5% was obtained. A short circuit current density (JSC) of 28 mA/cm2, an open-circuit voltage (VOC) of 1.288 V, and a fill factor (FF) of 87.7% were calculated. In addition, the developed model serves as a fitness function to optimize the light trapping capability using a multi-objective particle swarm optimization (MOPSO) approach. The optimized tandem solar cell design exhibits higher performance characterized by JSC =35.3 mA/cm2, VOC = 1.305 V, and a conversion efficiency of 41.7% which outweighs that of the conventional planar solar cell. Therefore, the proposed design methodology efficiently minimize the reflectance via establishing an intensive light trapping mechanism at the front of both subcells and opens promising opportunities to enhance the tandem solar cell performances
Simulation Study of Carbon Vacancy Trapping Effect on Low Power 4H-SiC MOSFET Performance
No full textThe carbon vacancy in 4H-SiC is an important recombination center of the minority carrier and a direct consequence of SiC-based device degradation. In 4H-SiC, this defect acts as the primary carrier-lifetime killer. Whether, low-energy electron radiation exposure or high temperature processing in an inert ambient gas will produce the carbon vacancy defect. Despite, the extensiveness of the studies concerning the defect’s modeling and characterization, numerous essential questions remain. Amongst them, we have the impact of these defects on the performance of 4H-SiC MOSFET. Herein, the influence of intrinsic defect states, namely, Z1/2 and EH6/7 centers, on the 4H-SiC MOSFET electrical outputs is examined via 2D numerical simulation. The obtained results show that the traps act to increase the device on-state resistance (RON), reduce the channel mobility, increase the threshold voltage (Vth). Besides, the increase of the temperature leads to less influence of the traps on the threshold variation. Furthermore, due to their locations in the bandgap, the impact of both Z1/2 and EH6/7 centers at room temperature on the device electrical outputs is extreme. For high temperature the EH6/7 have the severest impact because of the cross section temperature dependency
An optimized Graphene/4H-SiC/Graphene MSM UV-photodetector operating in a wide range of temperature
Get PDFn this paper, an accurate analytical model has been developed to optimize the performance of an Interdigitated Graphene Electrode/p-silicon carbide (IGE/p-4H-SiC) Metal semiconductor Metal (MSM) photodetector operating in a wide range of temperatures. The proposed model considers different carrier loss mechanisms and can reproduce the experimental results well. An overall assessment of the electrodes geometrical parameters’ influence on the device sensitivity and speed performances was executed. Our results confirm the excellent ability of the suggested Graphene electrode system to decrease the unwanted shadowing effect. A responsivity of 238 μA/W was obtained under 325-nm illumination compared to the 16.7 μA/W for the conventional Cr-Pd/p-SiC PD. A photocurrent to- dark-current ratio (PDCR) of 5.75 × 105 at 300 K and 270 at 500 K was distinguished. The response time was found to be around 14 μs at 300 K and 54.5 μs at 500 K. Furthermore, the developed model serves as a fitness function for the multi objective optimization (MOGA) approach. The optimized IGE/p-4H-SiC MSM-PD design not only exhibits higher performance in terms of PDCR (7.2 × 105), responsivity (430A/cm2) and detectivity (1.3 × 1014 Jones) but also balances the compromise between ultrasensitive and high-speed figures of merit with a response time of 4.7 μs. Therefore, the proposed methodology permits to realize ultra-sensitive, high-speed SiC optoelectronic devices for extremely high temperature applications
Analysis of the current–voltage–temperature characteristics of W/4H-SiC Schottky barrier diodes for high performance temperature sensors
No full textMultiobjective optimization of design of 4h-sic power mosfets for specific applications
No full textThe electrical characteristics of a 4H silicon carbide (4H-SiC) metal–oxide– semiconductor field-effect transistor (MOSFET) have been investigated by using a multiobjective genetic algorithm (MOGA) to overcome the existing tradeoff between main device figures of merit such as the breakdown voltage, drain current, and ON-state resistance. The aim of this work is to achieve an optimized device for a specific application. In particular, without loss of generality, we refer to a dual-implanted MOSFET (DMOSFET) dimensioned for use as a low-power transistor in direct current (DC)–DC converters for solar power optimizers. Typical blocking voltages for these transistors are around 150 V. In this investigation, both analytical and numerical models are used as objective functions in MOGA to determine a set of optimized physical and geometrical device parameters that meet the application constraints while minimizing the ON-state resistance (RON). The optimized DMOSFET exhibits an RON value of a few hundred kΩ × μm2 for different breakdown voltages in the range from 150 V to 800 V
Analysis of Al2O3 high-k gate dielectric effect on the electrical characteristics of a 4H-SiC low-power MOSFET
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